Demystifying Complex Workload-DRAM Interactions

Abstract

It has become increasingly difficult to understand the complex interactions between modern applications and main memory, composed of Dynamic Random Access Memory (DRAM) chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, memory access patterns of prevalent and emerging applications are rapidly diverging, as these applications manipulate larger data sets in very different ways. As a result, the combined DRAM-workload behavior is often difficult to intuitively determine today, which can hinder memory optimizations in both hardware and software. In this work, we identify important families of workloads, as well as prevalent types of DRAM chips, and rigorously analyze the combined DRAM-workload behavior. To this end, we perform a comprehensive experimental study of the interaction between nine different DRAM types and 115 modern applications and multiprogrammed workloads. We draw 12 key observations from our characterization, enabled in part by our development of new metrics that take into account contention between memory requests due to hardware design. Notably, we find that (1) newer DRAM technologies such as DDR4 and HMC often do not outperform older technologies such as DDR3, due to higher access latencies and, also in the case of HMC, poor exploitation of locality; (2) there is no single memory type that can effectively cater to all of the components of a heterogeneous system (e.g., GDDR5 significantly outperforms other memories for multimedia acceleration, while HMC significantly outperforms other memories for network acceleration); and (3) there is still a strong need to lower DRAM latency, but unfortunately the current design trend of commodity DRAM is toward higher latencies to obtain other benefits. We hope that the trends we identify can drive optimizations in both hardware and software design. To aid further study, we open-source our extensively-modified simulator, as well as a benchmark suite containing our applications.

Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling

“…As a result, there can be far more data lanes in an HBM channel (1024 per HBM stack) than a regular 64-bit DRAM channel, while each HBM channel is more efficient. Therefore, HBM provides at least an order of magnitude higher bandwidth than DDRx DRAM [15] at a lower power consumption (nearly 7pJ/bit as opposed to 25pJ/bit for a DDRx DRAM) with a smaller form factor [65].…”

“…Dynamic Random Access Memory (DRAM) is the predominant main memory technology used in traditional computing systems. With the significant growth in the computational capacity of modern systems, DRAM has become a power/performance/energy bottleneck, especially for data-intensive applications [12,15,37,38,39]. There are two approaches to alleviate this issue: (i) replacing DRAM with emerging technologies (e.g., Magnetic Memory (MRAM) [24,40] and Phase-Change Memory (PCM) [25,46,47]) and (ii) improving DRAM design (e.g., Reduced Latency DRAM (RLDRAM) [52], Graphics DDR (GDDR) [18], and Low-Power DDR (LPDDR) [33]).…”