2023
DOI: 10.1109/led.2023.3237598
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Demonstration of the β-Ga₂O₃ MOS-JFETs With Suppressed Gate Leakage Current and Large Gate Swing

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Cited by 14 publications
(5 citation statements)
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“…[105] The utilization of AOSs as active channel materials in TFTs has gained significant attention in recent years and demonstrated remarkable advances in terms of high μ, low offcurrent, low process temperature, versatile composition, and refined processing flexibility. Various AOSs have been extensively investigated, including In 2 O 3 , [106] Ga 2 O 3 , [107] ZnO, [108] ITO, [109] IGZO, [110] and HfInZnO, [111] with resulting publications available in the academic literature.…”
Section: Amorphous Oxide Semiconductor Tftsmentioning
confidence: 99%
“…[105] The utilization of AOSs as active channel materials in TFTs has gained significant attention in recent years and demonstrated remarkable advances in terms of high μ, low offcurrent, low process temperature, versatile composition, and refined processing flexibility. Various AOSs have been extensively investigated, including In 2 O 3 , [106] Ga 2 O 3 , [107] ZnO, [108] ITO, [109] IGZO, [110] and HfInZnO, [111] with resulting publications available in the academic literature.…”
Section: Amorphous Oxide Semiconductor Tftsmentioning
confidence: 99%
“…We have also analyzed the reasons why this effect is not reported or discussed in the lateral NiO/β-Ga 2 O 3 HJ-FET. 29,30,38,39 First of all, this electron confinement effect needs to be realized in E-mode HJ-FET so that appropriate positive bias can be applied to the gate. Subsequently, although the introduction of PN junctions enhances channel depletion, effective implementation of E-mode still requires relatively narrow channels, which results large channel resistance.…”
Section: Onspmentioning
confidence: 99%
“…on,sp But it is noted that the I D rise rate of Low E C Δ Fin-HJFET at V GS = 2.5 V is close to that of High E C Δ Fin-HJFET. And at this point the R on,sp is 3.1 m cm 2 Ω⋅ for Low E C Δ Fin-HJFET, which decreases a lot from 4.4 m cm 2 Ω⋅ at V GS = 2 V. Therefore, as the optimization adopted in the lateral HJ-FETs, 30,38 adding the gate dielectric to widen the gate swing is more essential to improve the performance of Low E C Δ Fin-HJFET. Alternatively, different from what we often pursue in heterojunction diodes, try to increase the V on of the heterojunction in Fin-HJFET.…”
Section: ω⋅mentioning
confidence: 99%
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“…One difficulty, however, is the increased gate leakage which occurs when the pn junction becomes forward-biased. A proposed solution, studied initially through TCAD simulations and verified using fabricated devices, is the addition of a dielectric layer between the p-NiO and gate metal to suppress gate leakage when the pn junction is forward-biased [76,235]. A 20 nm ALD-SiO 2 interlayer reduced the gate leakage by six orders of magnitude, maintained an on/off ratio of 10 6 , and improved the gate swing from 3 V to 13 V compared to the non-interlayer FET (Figure 18b).…”
Section: P-gatesmentioning
confidence: 99%