2002
DOI: 10.1142/s0218126602000410
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Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling

Abstract: A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated in this paper. It is shown that nonzero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a nonzero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays. Furthermore, a technique that significantly reduces the power… Show more

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Cited by 3 publications
(2 citation statements)
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“…The primary attributes of the multiplier; repetitive circuit elements, abutted or closely spaced layouts, extremely high throughput (i.e., many hundreds of megahertz) due to heavy pipelining, make the multiplier an important class of VLSI system that requires highly specialized clock distribution networks. [212], [213] The fundamental design trend in current microprocessors has been the development of systems operating at high clock frequencies; specifically, greater than 1-GHz operating frequencies. The primary difficulty in satisfying the goal of achieving these high clock rates is the delay uncertainty caused by process and environmental variations such as on-chip process parameter and temperature variations and related design-oriented issues such as voltage gradients, capacitive and inductive coupling, and load impedance mismatches.…”
Section: Bit 8 Bit Pipelined Multipliermentioning
confidence: 99%
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“…The primary attributes of the multiplier; repetitive circuit elements, abutted or closely spaced layouts, extremely high throughput (i.e., many hundreds of megahertz) due to heavy pipelining, make the multiplier an important class of VLSI system that requires highly specialized clock distribution networks. [212], [213] The fundamental design trend in current microprocessors has been the development of systems operating at high clock frequencies; specifically, greater than 1-GHz operating frequencies. The primary difficulty in satisfying the goal of achieving these high clock rates is the delay uncertainty caused by process and environmental variations such as on-chip process parameter and temperature variations and related design-oriented issues such as voltage gradients, capacitive and inductive coupling, and load impedance mismatches.…”
Section: Bit 8 Bit Pipelined Multipliermentioning
confidence: 99%
“…The application of clock skew scheduling has also been demonstrated on a similar microprocessor architecture in [213]. Both speed and power are enhanced through the use of clock skew scheduling.…”
Section: The Intel Ia-64 Microprocessormentioning
confidence: 99%