Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory

Stanisavljević, Miloš; Pozidis, Haralampos; Athmanathan, Aravinthan; Παπανδρεου, Νικολαοσ; Mittelholzer, T.; Eleftheriou, Evangelos

doi:10.1109/imw.2016.7495263

Cited by 39 publications

(22 citation statements)

References 8 publications

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“…Our methodology seeks to quantify the SCM design space model that we developed in §4, and validate the performance of our proposed memory hierarchy. Using our simulation infrastructure, we study a variety of combinations of row buffer sizes and read/write latencies that we gathered from device datasheets, industry projections, and published literature [8,48,67,69]. We then conduct a case study investigating the feasibility of four different PCM configurations from both performance and cost perspectives, based on the assumptions summarized in Table 2.…”

Section: Discussionmentioning

confidence: 99%

“…Figure 12 demonstrates that TLC-PCM can only satisfy the performance target with the largest possible 3D$, which brings the overall memory hierarchy's cost back in line with the baseline DRAM+3D$ system. Given its marginal improvement in performance/cost, as well as TLC's inherently worse endurance [67], we conclude that TLC-PCM is unable to act as a viable main memory technology for server applications. That conclusion is reinforced by the clear superiority of MLC-based alternatives.…”

Section: Case Study With Phase-change Memorymentioning

confidence: 95%

“…In this section, we trim the broad design space by identifying the key parameters that define SCM's performance in the context of our memory hierarchy. In general, the denser the SCM, the lower its cost per bit [48,57,67]. We therefore use SCM density as a proxy for SCM cost.…”

Section: Scm Cost/performance Tradeoff Explorationmentioning

confidence: 99%

“…The second approach, which we call MLC BW , favors higher bandwidth, resulting in write latencies of 1000ns and 1024B row buffers. Finally, we project the specifications of TLC-PCM based on a recent industrial prototype [8,67], and assume read and write latencies of 250ns and 2350ns, respectively. For the row buffer size, we optimistically assume 512B.…”

Section: Phase-change Memory Assumptionsmentioning

confidence: 99%

See 3 more Smart Citations

Design guidelines for high-performance SCM hierarchies

Ustiugov¹,

Daglis²,

Picorel

et al. 2018

Proceedings of the International Symposium on Memory Systems

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With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few factors of DRAM. Nevertheless, the latency-sensitive nature of memory-resident services makes seamless integration of SCM in servers questionable. In this paper, we ask the question of how best to introduce SCM for such servers to improve overall performance/cost over existing DRAM-only architectures. We first show that even with the most optimistic latency projections for SCM, the higher memory access latency results in prohibitive performance degradation. However, we find that deployment of a modestly sized high-bandwidth 3D stacked DRAM cache makes the performance of an SCM-mostly memory system competitive. The high degree of spatial locality that memory-resident services exhibit not only simplifies the DRAM cache's design as page-based, but also enables the amortization of increased SCM access latencies and the mitigation of SCM's read/write latency disparity.We identify the set of memory hierarchy design parameters that plays a key role in the performance and cost of a memory system combining an SCM technology and a 3D stacked DRAM cache. We then introduce a methodology to drive provisioning for each of these design parameters under a target performance/cost goal. Finally, we use our methodology to derive concrete results for specific SCM technologies. With PCM as a case study, we show that a two bits/cell technology hits the performance/cost sweet spot, reducing the memory subsystem cost by 40% while keeping performance within 3% of the best performing DRAM-only system, whereas single-level and triple-level cell organizations are impractical for use as memory replacements.• Information systems → Storage class memory; Cloud based storage; • Hardware → Memory and dense storage; KEYWORDS Storage-class memory, heterogeneous memory hierarchy, 3D stacked DRAM ACM Reference Format:

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Section: Discussionmentioning

confidence: 99%

Section: Case Study With Phase-change Memorymentioning

confidence: 95%

Section: Scm Cost/performance Tradeoff Explorationmentioning

confidence: 99%

Section: Phase-change Memory Assumptionsmentioning

confidence: 99%

See 2 more Smart Citations

Design guidelines for high-performance SCM hierarchies

Ustiugov¹,

Daglis²,

Picorel

et al. 2018

Proceedings of the International Symposium on Memory Systems

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“…The access time of HDD is limited to tens of milliseconds, which is 5-6 orders of magnitude slower than DRAM access time. However, with the recent advances in fast storage technologies such as NAND flash memory and NVM (non-volatile memory), the extremely wide speed gap has been reduced [2][3][4]. The typical access time of NAND flash memory is less than 50 milliseconds, and thus the speed gap between storage and memory is reduced to three orders of magnitude.…”

Section: Introductionmentioning

confidence: 99%

Implications of NVM Based Storage on Memory Subsystem Management

Bahn¹,

Cho

2020

Applied Sciences

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Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices.

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Emerging Memory Structures for VLSI Circuits

Garzón¹,

Yavits²,

Lanuzza³

et al. 2022

Wiley Encyclopedia of Electrical and Electronics Engineering

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Ever since the emergence of the electrical computer and the Von Neumann model, computer architects have adhered to a well‐structured hierarchy of memory solutions, clearly trading off performance and capacity with cost. The ubiquitous memory technologies, dominated by SRAM, DRAM, Flash, and magnetic hard disks, are each situated in a well‐defined location within this hierarchy. However, as processes have scaled into deep nanometer feature sizes and the demand for larger capacities and bandwidths increases, these traditional options face tough challenges and may be limited in their ability to continue to provide the new requirements. New technologies, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), have been researched and developed over the recent past in an attempt to meet these demands and replace some or all of the traditional technologies. In this article, the primary technologies are overviewed, including those that currently fill the memory hierarchy pyramid, the primary candidates to join or replace them in the near‐term, and a number of newer candidates that may arise as legitimate solutions in the farther term. In addition, an overview of the current state of processing within the emerging memory technologies is provided, as an attempt to break free of the traditional Von Neumann paradigm to overcome the energy and performance bottlenecks in modern systems.

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Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory

Cited by 39 publications

References 8 publications

Design guidelines for high-performance SCM hierarchies

Design guidelines for high-performance SCM hierarchies

Implications of NVM Based Storage on Memory Subsystem Management

Emerging Memory Structures for VLSI Circuits

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