Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories

Jan, Guenole; Thomas, Luc; Le, S.; Lee, Yuan-Jen; Liu, Huanlong; Zhu, Jianguo; Tong, Ru-Ying; Pi, K.; Wang, Yu-Jen; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Jeffrey W.; Lam, Vinh; Huang, Ko-Fan; Zhong, Tom; Torng, Terry; Wang, Po-Kang

doi:10.1109/vlsit.2014.6894357

Cited by 45 publications

(25 citation statements)

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“…large magnetoresistance. In addition to the advantages already mentioned, pMTJs offer long-term data storage even for nanopillar junctions just 10 nanometers in diameter and large tunnel magnetoresistance (TMR) [8][9][10].…”

mentioning

confidence: 99%

Sub-nanosecond spin-torque switching of perpendicular magnetic tunnel junction nanopillars at cryogenic temperatures

Rehm

Wolf²,

Kardasz³

et al. 2019

Applied Physics Letters

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Spin-transfer magnetic random access memory is of significant interest for cryogenic applications where a persistent, fast, low-energy consumption and high device density is needed. Here we report the low-temperature nanosecond duration spin-transfer switching characteristics of perpendicular magnetic tunnel junction (pMTJ) nanopillar devices (40 to 60 nm in diameter) and contrast them to their room temperature properties. Interestingly, at fixed pulse voltage overdrive the characteristic switching time decreases with temperature, in contrast to macrospin model predictions, with the largest reduction in switching time occurring between room temperature and 150 K. The switching energy increases with decreasing temperature, but still compares very favorably to other types of spin-transfer devices at 4 K, with < 300 fJ required per switch. Write error rate (WER) measurements show highly reliable (WER ≤ 5×10 -5 with 4 ns pulses at 4 K) demonstrating the promise of pMTJ devices for cryogenic applications and routes to further device optimization.

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mentioning

confidence: 99%

Sub-nanosecond spin-torque switching of perpendicular magnetic tunnel junction nanopillars at cryogenic temperatures

Rehm

Wolf²,

Kardasz³

et al. 2019

Applied Physics Letters

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“…It is worth noting that this work does not consider the cost related to error correction code (ECC) to minimize errors. However, it has been demonstrated that every cell out of a 8M b STT-MRAM chip could be written without the use of ECC down to a pulse length of 4.5ns [18].…”

Section: Main Memory Levelmentioning

confidence: 99%

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

et al. 2017

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Since the advent of complementary metal oxide semiconductors (CMOS), the number of transistor per die never stops increasing to reach today several billion of transistors. As a result, design and fabrication of smart devices able to run at high speed has been possible. However, the power consumption of systems-on-chip has significantly increased due to the high density integration and the high leakage power of current CMOS transistors. As a result, a heat dissipation wall makes difficult further improvement in performance. Having high autonomy for battery-powered devices becomes a real challenge. To deal with these issues, STT-MRAM technology is seen as a promising solution. In addition to its attractive performance features, STT-MRAM can bring non-volatility inside a system to allow full data retention after a complete shutdown while keeping a fast wake-up time. Considering two 32-bit embedded processors, this paper shows how STT-MRAM can improve energy efficiency and reliability of future embedded systems thanks to normally-off computing and checkpointing/rollback techniques. Finally, a detailed analysis is performed to evaluate the cost related to the backup/recovery of the system. Index Terms-Spintronic memory and logic, embedded processor.

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“…For simplicity purpose, NMOS is used to illustrate the effect of these assumptions. The ON resistance of a NMOS transistor in linear region can be expressed as (5), where it is shown to be proportional and inversely proportional to V GS and V D S , respectively, Fig. 4(a) shows the schematic of the normal and dummy cell current paths with NMOS selected as the column switches and selector.…”

Section: Validity and The Effect Of The Assumptionsmentioning

confidence: 99%

“…This type of emerging memory technology has been identified to be the candidate for future memory replacement [4]- [6]. Tremendous efforts have been devoted into materials engineering and nanofabrication to improve the devices' performance and uniformity, and many successful hardware prototypes of this technology in advanced CMOS process have been demonstrated [5]- [7]. However, the technology is still far from maturity and faces various fundamental challenges [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

An Optimized Resistance Characterization Technique for the Next Generation Magnetic Random Access Memory

Lua

Mani

2015

IEEE Trans. Nanotechnology

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This paper presents an accurate resistance characterization technique for magnetic random access memory (MRAM), such as STT-MRAM. By annulling the mismatch effect of CMOS transistors, this technique produces a resistance distribution profile of MRAM devices in a large array that reflects the actual device statistics. A 1 Kb array of MTJs with an intrinsic 3σ low resistance state distribution modeled with Verilog-A provides the reference device statistics. Monte Carlo simulation results of popular array configurations show the method's generic advantages of tightened distributions of the mean resistance value and standard deviation (SD) of the characterized 1 Kb devices than the reference method. Technology scaling study shows the sustainability of the proposed method with an improvement of the SD of the mean resistance distribution by at least 37.6%. The mean and SD of the standard deviation distribution were improved by at least 25.1% and 67.2% as compared to the reference method, respectively.

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Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories

Cited by 45 publications

References 1 publication

Sub-nanosecond spin-torque switching of perpendicular magnetic tunnel junction nanopillars at cryogenic temperatures

Sub-nanosecond spin-torque switching of perpendicular magnetic tunnel junction nanopillars at cryogenic temperatures

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

An Optimized Resistance Characterization Technique for the Next Generation Magnetic Random Access Memory

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