Demonstration of Dynamic Distributed Orchestration of Node-RED IoT Workflows Using a Vector Symbolic Architecture

Tomsett, Richard; Bent, Graham; Simpkin, Christopher; Taylor, Ian; Harbourne, Daniel; Preece, Alun; Ganti, Raghu

doi:10.1109/smartcomp.2019.00089

Cited by 6 publications

(2 citation statements)

References 7 publications

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“…HDC has been employed in a range of applications including cognitive computing [3], [4], robotics [5], distributed computing [6]- [8], communications [9]- [14], and in various aspects of machine learning. See [15] for a comprehensive review.…”

Section: Introductionmentioning

confidence: 99%

WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing

Guirado

Rahimi

Karunaratne

et al. 2023

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using long random vectors known as hypervectors. Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) has shown promise as it is very efficient in performing matrix-vector multiplications, which are common in the HDC algebra. Although HDC architectures based on IMC already exist, how to scale them remains a key challenge due to collective communication patterns that these architectures required and that traditional chip-scale networks were not designed for. To cope with this difficulty, we propose a scale-out HDC architecture called WHYPE, which uses wireless in-package communication technology to interconnect a large number of physically distributed IMC cores that either encode hypervectors or perform multiple similarity searches in parallel. In this context, the key enabler of WHYPE is the opportunistic use of the wireless network as a medium for overthe-air computation. WHYPE implements an optimized source coding that allows receivers to calculate the bit-wise majority of multiple hypervectors (a useful operation in HDC) being transmitted concurrently over the wireless channel. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. Through evaluations at the on-chip network and complete architecture levels, we demonstrate that WHYPE can bundle and distribute hypervectors faster and more efficiently than a hypothetical wired implementation, and that it scales well to tens of receivers. We show that the average error rate of the majority computation is low, such that it has negligible impact on the accuracy of HDC classification tasks.

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Section: Introductionmentioning

confidence: 99%

WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing

Guirado

Rahimi

Karunaratne

et al. 2023

IEEE J. Emerg. Sel. Topics Circuits Syst.

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show abstract

“…HDC has been employed in a range of applications such as cognitive computing [6]- [8], robotics [9], distributed com-puting [10]- [12], communications [13]- [18], and in various aspects of machine learning. It has shown significant promise in machine learning applications that especially demand fewshot learning [19]- [23], in-sensor adaptive learning [24], [25], multimodal learning [26], [27], and always-on smart sensing [28].…”

Section: Introductionmentioning

confidence: 99%

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Guirado¹,

Rahimi²,

Karunaratne³

et al. 2022

Preprint

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Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hypervectors). Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) systems have been recently proved to be one of the most energy-efficient options, due to hypervector manipulations in the memory itself that reduces data movement. Although implementations of HDC on single IMC cores have been made, their parallelization is still unresolved due to the communication challenges that these novel architectures impose and that traditional Networks-on-Chip and Networks-in-Package were not designed for. To cope with this difficulty, we propose the use of wireless on-chip communication technology in unique ways. We are particularly interested in physically distributing a large number of IMC cores performing similarity search across a chip, and maintaining the classification accuracy when each of which is queried with a slightly different version of a bundled hypervector. To achieve it, we introduce a novel over-the-air computing that consists of defining different binary decision regions in the receivers so as to compute the logical majority operation (i.e., bundling, or superposition) required in HDC. It introduces moderate overheads of a single antenna and receiver per IMC core. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. It is demonstrated that the proposed approach allows to both bundle at least three hypervectors and scale similarity search to 64 IMC cores seamlessly, while incurring an average bit error ratio of 0.01 without any impact in the accuracy of a generic HDC-based classifier working with 512-bit vectors.

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Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Guirado

Rahimi

Karunaratne

et al. 2022

2022 International Joint Conference on Neural Networks (IJCNN)

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Demonstration of Dynamic Distributed Orchestration of Node-RED IoT Workflows Using a Vector Symbolic Architecture

Cited by 6 publications

References 7 publications

WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing

WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing

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