Demonstration of A 3D Chip by Logic-DRAM Stacked Using Paired TSV Interconnection through Interface for AI/Edge-Computing Application

Lu, Chi; Chen, Chun Cheng; Lin, Sheng-Chieh; Chuang, Chih-Hao; Shih, Kai-Yao; Liao, Hsin-Yi; Huang, Chin-Hung; Ju, Ming‐Shaung; Ho, Cheng-Shu; Chen, Chi Ming; Chang, Shou-Zen

doi:10.1109/vlsi-tsa/vlsi-dat57221.2023.10134092

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT) 2023

DOI: 10.1109/vlsi-tsa/vlsi-dat57221.2023.10134092

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Demonstration of A 3D Chip by Logic-DRAM Stacked Using Paired TSV Interconnection through Interface for AI/Edge-Computing Application

Chi Lu

Chun Cheng Chen

Sheng-Chieh Lin

et al.

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Demonstration of A 3D Chip by Logic-DRAM Stacked Using Paired TSV Interconnection through Interface for AI/Edge-Computing Application

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