Demonstration of 108 Gb/s Duo-Binary PAM-8 Transmission and the Probabilistic Modeling of DB-PAM-M BER

Saber, Ghulam; Gutiérrez-Castrejón, R.; Xing, Zhenping; Alam, Samiul; El-Fiky, Eslam; Ceballos-Herrera, Daniel E.; Cavaliere, Fabio; Vall-llosera, Gemma; Lessard, Stéphane; Plant, David V.

doi:10.1109/jphot.2021.3054240

Cited by 7 publications

(6 citation statements)

References 29 publications

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“…In Figure 3, the red curve shows the power spectrum of the ideal DB channel, but it is obviously unrealistic to shape the full frequency band for a low-pass actual channel, so we use a low-pass filter to fit the DB channel. As shown by the blue line in Figure 3, with the combination of channel and CTLE is this type of Bessel low-pass filter [7], the processing result of the DB channel can also be satisfied. Although the high-frequency signal is lost, it is more conducive to implementation.…”

Section: Pre-equalization Processmentioning

confidence: 92%

“…At this time, the parameters of CTLE are fixed, and the DFE equalization value is used as the initial value of the next stage. In order to avoid error transmission during data transmission, precoding is required for DB-PAM4 data [7]: b k = (a k − b k−1 )mod4, bk precoded signal; ak is the original PAM4 signal. The precoded signal still belongs to the PAM4 type signal, and its corresponding z-domain expression is:…”

Section: Digital Equalization Processmentioning

confidence: 99%

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A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

Wang

Lai²,

Lyu³

et al. 2022

Electronics

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A high-speed serial interface is the core IP of a high-performance computer, data center and interconnection network; its bandwidth and bit error performance restrict the development of the system. With the evolution of high-speed serial interface line rates from 56 G to 112 G in high-end information systems, their bit errors increase sharply, limiting system performance. In order to solve the high-bit-error problem of the 112 Gb/s high-speed serial interface, this paper proposes a low-error Duo-binary PAM4 (DB-PAM) receive equalization technology. This technology utilizes the Duo-binary (DB) signal in which the channel and the transceiving equalizer work together to realize the low-error reception of the 112 Gb/s signal in the high-attenuation channel. To solve the problem of difficulty in generating high-speed DB-PAM4 signals and the complex adjustment of equalization parameters, this paper proposes a two-step progressive equalization technique. In the first step, the technology transmits not-return-to-zero (NRZ) signals at the transmitter (TX) and generates a Duo-binary (DB) signal path at the receiver using the least mean square error (LMS) algorithm. In the second step, the technology sends a precode-PAM4 (pre-PAM4) signal at TX; at the receiving end, the adaptive equalization algorithm is used to adjust the DSP equalization parameters to generate the optimal equalization parameters of the DB-PAM4 signal. This paper uses Cadence’s AMS simulation platform to verify the receive equalizer of DB-PAM4. Simulation results show: when a 112 Gb/s pre-PAM4 signal passes through the 35 dB@28 GHz channel, the receiver (RX) utilizes the adaptive equalizer to generate a 112 Gb/s DB-PAM4 signal, and the receiver bit error rate (BER) is less than 3e−9.

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Section: Pre-equalization Processmentioning

confidence: 92%

Section: Digital Equalization Processmentioning

confidence: 99%

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

Wang

Lai²,

Lyu³

et al. 2022

Electronics

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“…However, nextgeneration 5G and 6G systems will require even higher data rates, and PONs represent a suitable practical technology to support future optical access solutions [5][6][7][8]. Currently, research efforts are targeting data rates of 100 Gbps per λ and beyond [9][10][11][12][13][14][15][16][17] for the next step of PON evolution.…”

Section: Introductionmentioning

confidence: 99%

200 Gbps/λ PON Downstream C-Band Direct-Detection Links with ≥29 dB Power Budget

et al. 2022

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In this paper we present the simulative analysis of a 200 Gbps per wavelength (λ) 8-level pulse amplitude modulation (PAM-8) downstream communication over up to 20 km single mode fiber (SMF) in C-band based on direct detection (DD) achieving at least a 29 dB link power budget in a PON environment. We use chromatic dispersion digital pre-compensation (CD-DPC) and a dual-arm in-phase and quadrature Mach–Zehnder modulator (IQ-MZM) at the optical line termination (OLT) side, while preserving DD in the optical network unit (ONU). Three receiver digital-signal-processing (DSP) options are analyzed and compared: square-root-like technique (SQRT) in combination with a feed forward equalizer (FFE) and a decision feedback equalizer (DFE), the Volterra nonlinear equalizer (VNLE), and the SQRT in combination with the VNLE. The SQRT can be applied in combination with the VNLE to decrease the receiver DSP complexity while maintaining the required system performance. We show that PAM-8 with CD-DPC and the SQRT in combination with the VNLE is a feasible solution for 200 Gbps per λ downstream C-band transmission for PON.

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“…In the high-speed transmission of data, the NRZ (non return zero) modulation has a high attenuation in high-speed serial port applications above 112 Gb/s. Therefore, the PAM4 modulation has progressively been replacing the NRZ modulation, and its Nyquist frequency is half of that of the NRZ, which better solves the problem of data errors under a 70 dB strong channel attenuation [5,[8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

Tang

Shi

et al. 2022

Electronics

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To reduce the high bit error rate of serial transceivers under strong channel attenuation, a low-power 112 Gb/s SerDes transmitter was designed using a duo-binary PAM4 modulation technology. By adopting duo-binary PAM4 modulation technology, the problem of the low bandwidth utilization of a high-speed PAM4 (pulse amplitude modulation 4) signal was improved. The problem of high jitter caused by charge sharing and the limited bandwidth of a 4:1 high-speed MUX was improved by using precharging auxiliary transistors. The system power consumption of the transmitter was reduced by using a 7-bit weighted voltage-driven digital-to-analog converter (DAC). The transmitter was designed with a 28 nm CMOS process and powered by a voltage of 0.9 V. The simulation results showed that when the channel attenuation was 20.9 dB, the transmitter could work at 112 Gb/s, the power consumption was 2.02 pJ/bit, and the linearity was 96.7%.

show abstract

Demonstration of 108 Gb/s Duo-Binary PAM-8 Transmission and the Probabilistic Modeling of DB-PAM-M BER

Cited by 7 publications

References 29 publications

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

200 Gbps/λ PON Downstream C-Band Direct-Detection Links with ≥29 dB Power Budget

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

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