Delay test of chip I/Os using LSSD boundary scan

Gillis, P.S.; Woytowich, F.; McCauley, K.; Baur, U.

doi:10.1109/test.1998.743140

Cited by 36 publications

(7 citation statements)

References 15 publications

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“…Our technique is based on the ''I/O wrap delay'' measurement technique first described in [4] which used a precision-delayed strobe pulse generated by ATE or a proposed on-chip delay line; the strobe pulse was delivered to a capture latch with increasing delays until the captured result changed.…”

Section: Measuring I/o Delays Via Boundary Scanmentioning

confidence: 99%

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

Sunter¹,

Roy²

2012

IEEE Des. Test. Comput.

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Section: Measuring I/o Delays Via Boundary Scanmentioning

confidence: 99%

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

Sunter¹,

Roy²

2012

IEEE Des. Test. Comput.

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“…Boundary scanning has been used to test delay defects on I/O pads at wafer or package levels [3]; however, at-speed testing by multiple system clocks has not been properly addressed.…”

Section: Related Workmentioning

confidence: 99%

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

Yi¹,

Song²,

Park³

2008

ETRI Journal

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“…IOs tests will push stuck-at fault coverage to 99%. Transition tests for IOs can be generated using the method in [7].…”

Section: Fault Coverage Experimentsmentioning

confidence: 99%

At-Speed Structural Test For High-Performance ASICs

Iyengar

Yokota²,

Yamada³

et al. 2006

2006 IEEE International Test Conference

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At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-offscan clocking without the need to switch a scan enable atspeed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

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Delay test of chip I/Os using LSSD boundary scan

Cited by 36 publications

References 15 publications

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

At-Speed Structural Test For High-Performance ASICs

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