Delay-Line-Based Analog-to-Digital Converters

Li, Guansheng; Tousi, Yahya; Hassibi, Arjang; Afshari, Ehsan

doi:10.1109/tcsii.2009.2020947

Cited by 112 publications

(59 citation statements)

References 16 publications

(25 reference statements)

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“…The required convergence time is the minimum value of P for which the HDC logic is able to measure all the α k values with sufficient accuracy. Equation 9 gives insight into which terms affect the required converge time. For example, the mean squared estimation error for a given P gets worse as m increases.…”

Section: Harmonic Distortion Correction For Calibration Of Delay-linementioning

confidence: 99%

“…These effects impede analog circuit scaling [8,9]. In particular, the finite intrinsic gain of transistors makes designing an analog circuit more challenging.…”

Section: Introductionmentioning

confidence: 99%

“…Time-domain analog-to-digital conversion techniques, which include the voltage-to-time-to-digital approach and the voltage-to-delay-to-digital approach have recently become attractive, especially for deep submicron technologies [8,9,17]. The voltage-to-time-to-digital conversion utilizes a voltage-to-time converter and a time-to-digital converter (TDC) to digitalize input signal, shown in Figure 1(a).…”

Section: Introductionmentioning

confidence: 99%

“…Generally, time-domain ADCs benefit from the advances in fabrication technology. A GHz sampling rate can be easily achieved [9,17]. However, nonlinearity is still an issue, so that the resolution is hardly more than 4 bits with a hundred MHz sampling rate.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Lee

Abraham

2015

J Electron Test

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Delay line ADCs are becoming increasingly attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we first present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. In order to reduce the convergence time of the calibration, we inject a periodic 3-bit gray code sequence instead of three pseudorandom numbers for harmonic distortion correction to digitally calibrate an 8-bit delay line ADC. In our simulation results, the SNDR is significantly improved from 25.6 dB to 42.5 dB, with a calibration time of 13.5 milliseconds, which is 64X faster than harmonic distortion correction with the pseudorandom numbers.

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Section: Harmonic Distortion Correction For Calibration Of Delay-linementioning

confidence: 99%

“…These effects impede analog circuit scaling [8,9]. In particular, the finite intrinsic gain of transistors makes designing an analog circuit more challenging.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Lee

Abraham

2015

J Electron Test

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show abstract

“…Based on P-type and N-type voltage controlled delay cells [5], the time differences of different voltages can be derived, and hence the input voltage can be divided into 8 groups with 3-bit detection. The conventional TDC consists of a set of buffers and flip-flops.…”

Section: A Delay-line-based Enhanced Tuning Blockmentioning

confidence: 99%

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications

Huang

et al. 2013

2013 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the liftingbased searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18μm CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6μW power consumption and 0.032-mm 2 area. The FoM of this ADC is 49.4fJ/conversion-step.

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Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

Yeniceri

Yalçın

2015

Circuit Theory & Apps

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Summary In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look‐up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low‐pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field‐programmable gate array and utilized in a true random bit generator. Copyright © 2015 John Wiley & Sons, Ltd.

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Delay-Line-Based Analog-to-Digital Converters

Cited by 112 publications

References 16 publications

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

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