Delay Fault Coverage Increasing in Digital Circuits

Abstract

Delay faults testing is more and more critical due to huge number of gates and signal lines integrated on a chip. Path delay faults are tested via selected critical paths in a tested digital circuit but some critical paths can be found as untestable based on structure of the circuit. The circuit structure can be modified to increase the number of testable critical paths. Such modification brings added inputs and circuit area overhead. A new technique was proposed for circuit structure modification with the goal to decrease area overhead and number of additional inputs. This technique is based on usability of basic gates instead of multiplexers published till now. This DFT technique reduces the number of added logic gates used as test points involved on disconnected critical paths as previously published works. Evaluation of the proposed technique has been done over some selected benchmark circuits and compared with published results.

Faster synthesis of combinational logic based on multiplexer trees and binary decision diagrams

“…Functional blocks, as blocks which contain also multiplexers, can be easily disconnected from power supply based on designed power architecture integrated in a system-level model [8]. Multiplexers are also used in combinational circuit redesign for increasing quality of time specification testing and therefore they have to be involved there in optimal overhead or another logic gates have to be used [9]. Multiplexers are also used in selftesting or self-repairing memories [10] where it is important to minimize their usability in controlling test and functional modes and also power consumption.…”