Delay and Power Analysis of Three Coupled through Silicon Vias in 3D ICs

Abstract

3D IC is developing as an incredible response for the next generation system packaging and integration technology to accomplish low power utilization, high channel transfer speed and high-density integration capability simultaneously. With respect to the vertical interconnect for a 3D IC, through-silicon via (TSV) is a key part which can produce a myriad performance improvement with the extraordinarily decreased length of interconnects among vertically stacked dies. In this paper, the electrical equivalent model of a TSV is proposed and the electrical behaviour of three coupled TSV with the variation of length, diameter, and pith parameters are analysed.