Delay and Area Efficient First-level Cache Soft Error Detection and Correction

Mohr, K.C.; Clark, Lawrence T.

doi:10.1109/iccd.2006.4380799

Cited by 29 publications

(9 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Mohr and Clark [25] employed two-dimensional parity schemes to detect and correct single bit errors within a word. They applied product codes to memory arrays and used horizontal byte-parity codes to enable low-latency error detection with a minimal increase in area.…”

Section: Low-cost Eccmentioning

confidence: 99%

“…Previous studies showed that single-error correction and doubleerror detection (SEC-DED) in L1 cache would increase its access latency by up to 95%, power consumption by up to 22%, and area cost by up to 18% [22][23][24] . A variety of techniques have been proposed to reduce the area, performance and power costs of ECC [25][26][27][28][29][30] .…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Cheng

Zhang

2011

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor (AVF) has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e., issue queue, reorder buffer). Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes (ECC). However, protecting caches closer to the processor (i.e., L1 data cache (L1D)) using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dynamic vulnerability behavior of L1D and detect the correlations between L1D AVF and various performance metrics. We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF. Then, we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics, thus enabling a simplified and fast estimation of L1D AVF. Based on the simplified and fast estimation of L1D AVF, intervals of high L1D AVF can be identified online, enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC. Experimental results show that compared with traditional ECC technique which provides complete ECC protection throughout the entire lifetime of a program, AVF-aware ECC technique reduces the L1D access latency by 35% and saves power consumption by 14% for SPEC2K benchmarks averagely.

show abstract

Section: Low-cost Eccmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Cheng

Zhang

2011

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…A variety of techniques have been proposed to reduce the costs of ECC [20]- [24]. However, all these techniques assumed that the probability a soft error would result in an erroneous program outcome (i.e., AVF [9]) is 100%, and therefore provide full ECC protection throughout the entire execution lifetime of programs.…”

Section: Introductionmentioning

confidence: 99%

Accurate and Simplified Prediction of L2 Cache Vulnerability for Cost-Efficient Soft Error Protection

Cheng

Zhang

2012

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYSoft errors caused by energetic particle strikes in on-chip cache memories have become a critical challenge for microprocessor design. Architectural vulnerability factor (AVF), which is defined as the probability that a transient fault in the structure would result in a visible error in the final output of a program, has been widely employed for accurate soft error rate estimation. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e., issue queue, reorder buffer). Considering large on-chip L2 cache, redundancy-based protection techniques (such as ECC) have been widely employed for L2 cache data integrity with high costs. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to the over-protection, thus incurring high overheads. Therefore, designing AVF-aware protection techniques would be attractive for designers to achieve a cost-efficient protection for caches, especially at early design stage. In this paper, we propose an improved AVF estimation framework for conducing comprehensive characterization of dynamic behavior and predictability of L2 cache vulnerability. We propose to employ Bayesian Additive Regression Trees (BART) method to accurately model the variation of L2 cache AVF and to quantitatively explain the important effects of several key performance metrics on L2 cache AVF. Then we employ bump hunting technique to extract some simple selecting rules based on several key performance metrics for a simplified and fast estimation of L2 cache AVF. Using the simplified L2 cache AVF estimator, we develop an AVF-aware ECC technique as an example to demonstrate the cost-efficient advantages of the AVF prediction based dynamic fault tolerant techniques. Experimental results show that compared with traditional full ECC technique, AVF-aware ECC technique reduces the L2 cache access latency by 16.5% and saves power consumption by 11.4% for SPEC2K benchmarks averagely.

show abstract

“…This scheme detects and corrects single-bit errors within a memory array. Mohr [32] also applies product codes to memory arrays and uses horizontal byte-parity codes to enable low-latency error detection. The proposed 2D coding in this paper similarly achieves the area-efficient protection by applying only a single strong error correcting code to the entire array.…”

Section: Related Workmentioning

confidence: 99%