Delay analysis of CMOS gates using modified logical effort model

Kabbani, A.; Al-Khalili, D.; Al-Khalili, A.J.

doi:10.1109/tcad.2005.847892

Cited by 23 publications

(12 citation statements)

References 12 publications

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“…The slope-correction model is based on (2) and is much simpler than the models in [5] and [6]. However, due to the nonlinear relationship between input slope and delay, the linear models are not very accurate when the input transitions are slow.…”

Section: A Proposed Slope-correction Modelmentioning

confidence: 99%

“…In more recent years, many have modified the original logical-effort model to better model the input slope effect, along with the switching behavior, input-output coupling capacitance, mobility degradation, and velocity saturation effects [5], [6]. However, [5] requires a few SPICE model parameters and three additional fitting parameters, along with a nonlinear model for the input slope effect involving recursive calculations.…”

Section: Introductionmentioning

confidence: 99%

“…However, [5] requires a few SPICE model parameters and three additional fitting parameters, along with a nonlinear model for the input slope effect involving recursive calculations. The model in [6] adds three additional terms to (1), and each term is based upon complex calculations from the SPICE model. Although [5] and [6] both have an average modeling error of <5%, their usage is limited to synthesis tools due to their modeling complexity, and there is yet to be a solution feasible for hand analysis.…”

Section: Introductionmentioning

confidence: 99%

“…The model in [6] adds three additional terms to (1), and each term is based upon complex calculations from the SPICE model. Although [5] and [6] both have an average modeling error of <5%, their usage is limited to synthesis tools due to their modeling complexity, and there is yet to be a solution feasible for hand analysis.…”

Section: Introductionmentioning

confidence: 99%

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Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction

Wang

Marković

2009

IEEE Trans. Circuits Syst. II

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This brief presents an improved logical-effort model to account for the slope mismatch between the input and output of a gate. The model has a simple formulation in which only one additional parameter is needed, making the analysis suitable for hand calculations. Using 65-and 90-nm complementary metal-oxide-semiconductor technologies, the model maintains less than 5% error in gate-delay estimations compared to Spectre simulations even under large variations between the input and output slopes. Using this model, a circuit optimization tool is written to optimize an adder synthesized with a 65-nm standardcell library. The estimation error for the adder is also within the modeling accuracy of 5%, whereas the original logical-effort model and the synthesis timing libraries have errors of up to 40% and 20%, respectively.

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Section: A Proposed Slope-correction Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction

Wang

Marković

2009

IEEE Trans. Circuits Syst. II

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“…These ramps are assumed to have the same starting and ending points and are referred as normalized inputs. Normalized inputs are required to solve the differential equations describing the circuit operation [1,[4][5][6]. Parallel transistors, of the same width, with normalized inputs can be replaced by one transistor that has the normalized ramp as input while its width is equal to the sum of the widths of the parallel transistors [7].…”

Section: Introductionmentioning

confidence: 99%

Input mapping algorithm for parallel transistor structures

Nikolaidis

2008

Circuit Theory & Apps

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SUMMARYA new algorithm for mapping every possible input pattern of a parallel transistor structure to an equivalent set of normalized inputs (having the same starting and ending point) is introduced. This algorithm is based on the analysis of the operation of the transistor structure and can be used for the development of analytical timing models for CMOS circuits. Simulation results show a very good accuracy of the algorithm.

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