Degradation of static behaviour of poly-Si CMOS inverters under high frequency operation

Abstract

We studied the degradation of poly-Si CMOS inverters under high frequency operation. Increased low noise margin and logic threshold voltage, decreased high noise margin and gain were observed. Based on a previous drain current model of thinfilm transistors (TFTs), voltage transfer characteristic of inverter is well described. Large degradation was observed in p-TFT instead of n-TFT after 10 ks operation. Dynamic negative bias temperature instability is considered to be the degradation mechanism leading to the inverter's degradation.