Degradation of Off-Phase Leakage Current of FinFETs and Gate-All-Around FETs Induced by the Self-Heating Effect in the High-Frequency Operation Regime

Park, Chuntaek; Yun, Ilgu

doi:10.1109/tnano.2020.2986540

Cited by 7 publications

(3 citation statements)

References 12 publications

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“…Extension work to establish the precise device models for 3D devices such as Fin-FETs [30][31][32] or gate-all-around FETs [33,34] is still outstanding. Even though the device format is multi-nano-sheet (mNS) or multi-bridge-channel [16,[35][36][37], this concept of providing a great set of device models considering the contribution of the gate field is rather feasible.…”

Section: Discussionmentioning

confidence: 99%

Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

Chao

Huang

et al. 2022

Crystals

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A novel channel mobility model with two-dimensional (2D) aspect is presented covering the effects of source/drain voltage (VDS) and gate voltage (VGS), and incorporating the drift and diffusion current on the surface channel at the nano-node level, at the 28-nm node. The effect of the diffusion current is satisfactory to describe the behavior of the drive current in nano-node MOSFETs under the operations of two-dimensional electrical fields. This breakthrough in the model’s establishment opens up the integrity of long-and-short channel devices. By introducing the variables VDS and VGS, the mixed drift and diffusion current model effectively and meaningfully demonstrates the drive current of MOSFETs under the operation of horizontal, vertical, or 2D electrical fields. When comparing the simulated and experimental consequences, the electrical performance is impressive. The error between the simulation and experiment is less than 0.3%, better than the empirical adjustment required to issue a set of drive current models.

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Section: Discussionmentioning

confidence: 99%

Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

Chao

Huang

et al. 2022

Crystals

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“…However, the introduction of hightopology 3D devices, such as FinFET and Nanosheet, is not conducive to the heat dissipation of the hot spot, exacerbating the self-heating effect (SHE). [1][2][3][4][5] Moreover, the SHE can not only lead to a decline in the fundamental electrical performance, such as threshold voltage shift (Vth) drift and subthreshold swing (SS) degradation, 6,7) but also decrease the device reliability, reducing the operating lifetime of the device and circuit. [8][9][10][11] With the size-shrinking of nano-devices and the requirement to reduce the layout scale further, the entire 3D complementary FET (CFET) devices with the following advantages and innovations are introduced: [12][13][14][15] (1) A higher degree of integration and less area occupation than the previous CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

Self-heating effect on logic performance of 6T-SRAM based on CFET device

Zhao

Liu

et al. 2022

Jpn. J. Appl. Phys.

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CFET devices have become emerging and promising candidates for continuing Moore's law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the SRAM unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

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“…This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, several CMOS-like structures such as the nanowire gate all around MOSFETs (Kumar et al , 2019; Park and Yun, 2020; Agarwal et al , 2019), FinFETs (Khandelwal et al , 2014; Bha et al , 2020; Singh, 2018), carbon nanotube field effect transistor (Ho et al , 2019; Tamersit, 2019a, 2019b), impact ionization field effect transistors (FETs) (Lal et al , 2018; Lahgere and Kumar, 2017; Thornton et al , 2016) and Tunnel FETs (TFETs) (Choi and Lee, 2010; Kumar, 2017) were demonstrated by various research groups, to minimize the short channel effects (SCEs) and to lower the source-drain leakage current. Among these devices, only TFET and I-MOSFET promise a subthreshold swing less than 60 mV/dec and improved short channel performance, which is attributed to fundamentally a different mechanism used for carrier injection from source to channel.…”

Section: Introductionmentioning

confidence: 99%

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Ghosh

Venkateswaran

Sarkar

2021

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Purpose High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit. Design/methodology/approach Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances. Findings The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter. Originality/value Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

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Degradation of Off-Phase Leakage Current of FinFETs and Gate-All-Around FETs Induced by the Self-Heating Effect in the High-Frequency Operation Regime

Cited by 7 publications

References 12 publications

Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

Self-heating effect on logic performance of 6T-SRAM based on CFET device

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

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