Defining and translating a "safe" subset of simulink/stateflow into lustre

Scaife, Norman; Sofronis, Christos; Caspi, Paul; Tripakis, Stavros; Maraninchi, Florence

doi:10.1145/1017753.1017795

Cited by 85 publications

(59 citation statements)

References 18 publications

(34 reference statements)

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“…In this section, we describe a small subset of the Stateflow features used in the translation procedure. A detailed description can be found in [14], [11].…”

Section: Brief Overview Of Stateflowmentioning

confidence: 99%

“…This allows the use of Simulink toolboxes for simulation and code synthesis for controllers verified in UPPAAL, and is a step towards a modular code synthesis. Although there exist different tools for translation of Stateflow models into various frameworks (e.g., [11]), to the best of our knowledge, this is the first tool for translation of UPPAAL models into Stateflow.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

From Verification to Implementation: A Model Translation Tool and a Pacemaker Case Study

Pajić

Jiang

Lee

et al. 2012

2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium

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Model-Driven Design (MDD) of cyber-physical systems advocates for design procedures that start with formal modeling of the real-time system, followed by the model's verification at an early stage. The verified model must then be translated to a more detailed model for simulation-based testing and finally translated into executable code in a physical implementation. As later stages build on the same core model, it is essential that models used earlier in the pipeline are valid approximations of the more detailed models developed downstream. The focus of this effort is on the design and development of a model translation tool, UPP2SF, and how it integrates system modeling, verification, model-based WCET analysis, simulation, code generation and testing into an MDD based framework. UPP2SF facilitates automatic conversion of verified timed automata-based models (in UPPAAL) to models that may be simulated and tested (in Simulink/Stateflow). We describe the design rules to ensure the conversion is correct, efficient and applicable to a large class of models. We show how the tool enables MDD of an implantable cardiac pacemaker. We demonstrate that UPP2SF preserves behaviors of the pacemaker model from UPPAAL to Stateflow. The resultant Stateflow chart is automatically converted into C and tested on a hardware platform for a set of requirements. Abstract-Model-Driven Design (MDD) of cyber-physical systems advocates for design procedures that start with formal modeling of the real-time system, followed by the model's verification at an early stage. The verified model must then be translated to a more detailed model for simulation-based testing and finally translated into executable code in a physical implementation. As later stages build on the same core model, it is essential that models used earlier in the pipeline are valid approximations of the more detailed models developed downstream. The focus of this effort is on the design and development of a model translation tool, UPP2SF, and how it integrates system modeling, verification, model-based WCET analysis, simulation, code generation and testing into an MDDbased framework. UPP2SF facilitates automatic conversion of verified timed automata-based models (in UPPAAL) to models that may be simulated and tested (in Simulink/Stateflow). We describe the design rules to ensure the conversion is correct, efficient and applicable to a large class of models. We show how the tool enables MDD of an implantable cardiac pacemaker. We demonstrate that UPP2SF preserves behaviors of the pacemaker model from UPPAAL to Stateflow. The resultant Stateflow chart is automatically converted into C and tested on a hardware platform for a set of requirements.

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“…In this section, we describe a small subset of the Stateflow features used in the translation procedure. A detailed description can be found in [14], [11].…”

Section: Brief Overview Of Stateflowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

From Verification to Implementation: A Model Translation Tool and a Pacemaker Case Study

Pajić

Jiang

Lee

et al. 2012

2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium

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show abstract

“…The main drawback is that it provides an obscure semantic in which the behavior may depend on strange features such as, for instance, the lexicographic order of block names or the graphical position of blocks in a drawing [12].…”

Section: Synchrony As a Programming Paradigmmentioning

confidence: 99%

Synchronous Programming

Caspi¹,

Tripakis²,

Raymond³

2007

Chapman &Amp; Hall/CRC Computer &Amp; Information Science Series

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“…The ZET semantics is close to the semantics of modeling tools such as Simulink , which are used to develop and simulate controller designs. ZET programming therefore enables model-based design of embedded control systems in the sense that control models may directly be translated into executable ZET programs [29]. Moreover, ZET programs may be verified for functional correctness because most ZET programming languages have formal semantics.…”

Section: Program 13: a Periodic Task H Sharing Its State Using A Mutmentioning

confidence: 99%