Defect reduction in heteroepitaxial InP on Si by epitaxial lateral overgrowth

Abstract

Epitaxial lateral overgrowth of InP has been grown by hydride vapor phase epitaxy on Si substrates with a thin seed layer of InP masked with SiO 2 . Openings in the form of multiple parallel lines as well as mesh patterns from which growth occurred were etched in the SiO 2 mask and the effect of different growth conditions in terms of V/III ratio and growth temperature on defects such as threading dislocations and stacking faults in the grown layers was investigated. The samples were characterized by cathodoluminescence and by transmission electron microscopy. The results show that the cause for threading dislocations present in the overgrown layers is the formation of new dislocations, attributed to coalescence of merging growth fronts, possibly accompanied by the propagation of pre-existing dislocations through the mask openings. Stacking faults were also pre-existing in the seed layer and propagated to some extent, but the most important reason for stacking faults in the overgrown layers was concluded to be formation of new faults early during growth. The formation mechanism could not be unambiguously determined, but of several mechanisms considered, incorrect deposition due to distorted bonds along overgrowth island edges was found to be in best agreement with observations.

Study of planar defect filtering in InP grown on Si by epitaxial lateral overgrowth

“…Indeed, this is also what has been observed experimentally [29,30], though stacking faults bounded by partials in the <112> directions in GaAs on Si has also been observed [31]. Also, in a recent study, SF width increased with layer thickness in a way suggesting a 60° angle at most between the bounding partials, suggesting that the bounding partials lie in the <101> and <011> directions [25].…”

“…With the distance 400 nm constituting the base of the triangle and the angle between the [110] direction and the opening being 30°, the height of the triangle corresponding to the distance in the [110] direction becomes 400/tan(30°) = 692.8… ~700 nm. Since most of the stacking faults are extending from the interface between the Si substrate and the roughly 4 µm thick seed layer, they would thus have a width of around the same size at the seed layer surface since the increase in stacking fault width has previously been found to scale with layer thickness with a relation of roughly 1:1 [25]. Consequently, it is probable that SF4 and SF5 are indeed exposed in the opening at some point.…”

“…Besides, thermal annealing prior to ELOG may be able to further relax residual strain in the seed layer, thus potentially removing the cause for the stacking fault formation in the first place. Although annealing would mean raising the temperature above the growth temperature thus in theory leading to a greater strain from the Si substrate, this thermal strain does not appear to be a major factor in the formation of stacking faults since a higher temperature during ELOG lead to a lower density of stacking faults [25]. The propagating and non-propagating stacking faults are shown in Fig.…”

Optical and structural properties of sulfur-doped ELOG InP on Si

“…In the previous work, the average sulfur doping concentration in the coalesced ELOG InP layers on Si was measured by Hall measurements to be $2 Â 10 18 cm À3 . 20 The observed less effective impurity hardening in this work and the occurrence of stacking faults in HVPE regrown InP seed could be due to a lower sulfur concentration in planar InP growth, which is not sufficient to introduce the impurity hardening effect. The propagation and expansion of stacking faults in ELOG that originate from the seed can be explained by the impact of impurity on the stacking faults, which are governed by the Suzuki segregation effect.…”

“…Such wide stacking faults are indeed observed in the planview micrographs of the ELOG InP grown Si. 20 The partial dislocations bounding the faults can extend over the mask along the fault plane, which results in the stacking faults circumventing the SiO 2 masks during ELOG InP as observed in XTEM characterization images (Figs. 7-10).…”