Defect-oriented testing of mixed-signal ICs: some industrial experience

Xing, Yizi

doi:10.1109/test.1998.743212

Cited by 29 publications

(13 citation statements)

References 13 publications

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“…The CPU time of the golden stand-alone simulation is 244s. The CPU time of the Standard AS/DOTSS approach [16] is calculated in the usual way (#faults * CPU time of golden = 412 * 244s = 100437s). The CPU time mostly depends on how many measurement time points are set.…”

Section: Results Ffs With Sensitivity Predictionmentioning

confidence: 99%

Robust DC and efficient time-domain fast fault simulation

Tasic

Dohmen

Maten

et al. 2014

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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Purpose -Imperfactions in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the effciency of these simulations. Design/methodology/approach -Determining the DC solution can be very hard. For this we present an adaptive time domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and efficient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. Finding -We fully exploit the hierarchical structure the circuit in the simulation process to bypass parts of the circuit that appear to be unaffected by the fault. Accurate prediction and efficient solution procedures lead to fast fault simulation. Originality/value -Our fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output "matches" a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very efficient.

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Section: Results Ffs With Sensitivity Predictionmentioning

confidence: 99%

Robust DC and efficient time-domain fast fault simulation

Tasic

Dohmen

Maten

et al. 2014

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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show abstract

“…Any random defects that affect one or more building blocks within the loop will likely cause fail-to-lock condition. Other methods presented in the literature, such as the structural-based test approach for RF devices in [11] and the defect-oriented test methods for mixed-signal circuits in [12], can effectively detect catastrophic failures at a relatively low cost. We can apply these simple tests first in our test application and terminate the test process once a failure is detected.…”

Section: Test Applicationmentioning

confidence: 99%

Test cost reduction through performance prediction using virtual probe

Chang

Cheng

Zhang

et al. 2011

2011 IEEE International Test Conference

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-The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on their statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with more than 50 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. In this example, the 3σ error of VP prediction is less than 12% for predictable or highly predictable test items. Applying the VP technique can on average replace 59% of test measurement by prediction and, consequently, reduce the overall test time by 57.6%.

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“…As explained before [2,3], there are methods to identify slightly deviating products, for instance by making use of moving limits. For effective EOS/ESD screens, pins are identified that are typically seen as affected in EOS/ESD returns, and analogue tests are identified that would be influenced by an additional resistance path at the typical EOS/ESD location.…”

Section: Continuous Eos/esd Return Reductionmentioning

confidence: 99%

Automotive IC reliability: Elements of the battle towards zero defects

Kuper

2008

Microelectronics Reliability

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Defect-oriented testing of mixed-signal ICs: some industrial experience

Cited by 29 publications

References 13 publications

Robust DC and efficient time-domain fast fault simulation

Robust DC and efficient time-domain fast fault simulation

Test cost reduction through performance prediction using virtual probe

Automotive IC reliability: Elements of the battle towards zero defects

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