Defect generation at the Si–SiO2 interface following corona charging

Jin, Hao; Weber, Klaus; Dang, Nhan C.; Jellett, Wendy

doi:10.1063/1.2749867

Cited by 28 publications

(23 citation statements)

References 15 publications

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“…For example, the midgap interface defect density of c-Si can be as low as ~ 1×10 9 eV -1 cm -2 after the introduction of a thermal SiO 2 film and a subsequent annealing. 27 The AAP processing in this study is analogous to this approach.…”

Section: Resultsmentioning

confidence: 97%

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters

Luo

Liang

Cao

et al. 2015

ACS Appl. Mater. Interfaces

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For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

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Section: Resultsmentioning

confidence: 97%

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters

Luo

Liang

Cao

et al. 2015

ACS Appl. Mater. Interfaces

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“…It is observed that s eff (Dn) is notably downshifted, which strongly suggests that the deposition of corona charges is invasive in this case. Corona charging generates additional interface traps, and Jin et al 38 pointed out that such interface deterioration is unavoidable even at low electric fields. Such interface damage in corona charging makes the interpretation of the results more difficult as the poorer interface passivation reduces the difference seen in Fig.…”

Section: Polarity Inversion Experimentsmentioning

confidence: 99%

Advanced modeling of the effective minority carrier lifetime of passivated crystalline silicon wafers

Samudra

Peters

et al. 2012

Journal of Applied Physics

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Articles you may be interested inThe effect of light soaking on crystalline silicon surface passivation by atomic layer deposited Al2O3 J. Appl. Phys. 113, 024509 (2013); 10.1063/1.4775595 Minority charge carrier lifetime mapping of crystalline silicon wafers by time-resolved photoluminescence imaging J. Appl. Phys. 110, 054508 (2011); 10.1063/1.3630031 High effective minority carrier lifetime on silicon substrates using quinhydrone-methanol passivation Appl. Phys. Lett. 96, 063502 (2010); 10.1063/1.3309595 Impact of metal-oxide gate dielectric on minority carrier lifetime in siliconA strong injection level dependence of the effective minority carrier lifetime (s eff ) is typically measured at low injection levels for undiffused crystalline silicon (c-Si) wafers symmetrically passivated by a highly charged dielectric film. However, this phenomenon is not yet well understood. In this work, we concentrate on two of those possible physical mechanisms to reproduce measured s eff data of c-Si wafers symmetrically passivated by atomic layer deposited Al 2 O 3 . The first assumes the existence of a defective region close to the c-Si surface. The second assumes asymmetric electron and hole lifetimes in the bulk. Both explanations result in an adequate reproduction of the injection dependent s eff found for both n-and p-type c-Si wafers. However, modeling also predicts a distinctly different injection dependence of s eff for the two suggested mechanisms if the polarity of the effective surface charge is inverted. We test this prediction by experimentally inverting the polarity of the effective surface charge using corona charges. From the experiments and simulations, it is concluded that surface damage is the most likely cause of the significant reduction of s eff at low injection levels. V C 2012 American Institute of Physics. [http://dx.

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“…For example, the midgap interface defect density of c-Si can be as low as 1 ϫ 10 9 eV −1 cm −2 after the growth of a high quality thermal SiO 2 film and a subsequent anneal in a H 2 atmosphere, e.g., a forming gas anneal. 6 The second strategy to reach surface passivation is based on a significant reduction of the electron or hole concentra-tion at the semiconductor interface by means of a built-in electric field. As recombination processes require both electrons and holes, the highest recombination rate is obtained when the electron and hole concentration at the interface are approximately equal in magnitude ͑assuming identical capture cross sections for electrons and holes͒.…”

Section: Introductionmentioning

confidence: 99%

On the c-Si surface passivation mechanism by the negative-charge-dielectric Al2O3

Hoex

Gielis

Sanden

et al. 2008

Journal of Applied Physics

520

421

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Defect generation at the Si–SiO2 interface following corona charging

Abstract: Published by the AIP Publishing Articles you may be interested inOn the c -Si surface passivation mechanism by the negative-charge-dielectric Al 2 O 3

Cited by 28 publications

References 15 publications

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters

Advanced modeling of the effective minority carrier lifetime of passivated crystalline silicon wafers

On the c-Si surface passivation mechanism by the negative-charge-dielectric Al2O3

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