Deeply-scaled GaN-on-Si high electron mobility transistors with record cut-off frequency <i>f</i> <sub>T</sub> of 310 GHz

Xie, Huimin; Liu, Zhihong; Gao, Yu; Ranjan, Kumud; Lee, Kenneth E.; Ng, Geok Ing

doi:10.7567/1882-0786/ab56e2

Cited by 29 publications

(20 citation statements)

References 32 publications

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“…Benchmark of cut-off frequency versus L G [143][144][145][146][147][148] illustrates the importance of gate length shrinking to increase f T . Both NTU [149] and Intel [143] demonstrated 40 nm gate length GaN HEMT on Si with f T /fmax higher than 300 GHz, though the current record f T /fmax values of 450 GHz was achieved by HRL [144] with the 20 nm Gate GaN on SiC technology. GaN HEMT on Si also have high load pull result comparable to SiC substrate [155], nevertheless, GaN HEMT on Si substrate shows high potential.…”

Section: Rf Gan Performance Si Substratementioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

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GaN HEMT has attracted a lot of attention in recent years owing to its wide applications from the high-frequency power amplifier to the high voltage devices used in power electronic systems. Development of GaN HEMT on Si-based substrate is currently the main focus of the industry to reduce the cost as well as to integrate GaN with Si-based components. However, the direct growth of GaN on Si has the challenge of high defect density that compromises the performance, reliability, and yield. Defects are typically nucleated at the GaN/Si heterointerface due to both lattice and thermal mismatches between GaN and Si. In this article, we will review the current status of GaN on Si in terms of epitaxy and device performances in high frequency and high-power applications. Recently, different substrate structures including silicon-on-insulator (SOI) and engineered poly-AlN (QST®) are introduced to enhance the epitaxy quality by reducing the mismatches. We will discuss the development and potential benefit of these novel substrates. Moreover, SOI may provide a path to enable the integration of GaN with Si CMOS. Finally, the recent development of 3D hetero-integration technology to combine GaN technology and CMOS is also illustrated.

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Section: Rf Gan Performance Si Substratementioning

confidence: 99%

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Hsu

Lai

et al. 2021

Micromachines

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“…Xie et al reported f T / f max of 310/40 GHz with L G = 40 nm, but with an R C of 0.16–0.18 Ω mm using alloyed Ohmic contacts. [ 10 ] While the trends in f T reported in these devices are observed to increase, the effective electron velocity is still far from the theoretical limits. A high effective electron velocity and a low parasitic delay result in a good f T –L G product in a device.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, GaN‐on‐SiC wafer size being limited to 6 inch is a bottleneck in scalability and hence, GaN‐on‐Si HEMTs are being increasingly explored for radio frequency (RF) and power performance. [ 5–13 ]…”

Section: Introductionmentioning

confidence: 99%

20.2 GHz‐µmf_T–L_Gin InAlN/GaN‐on‐Si High Electron Mobility Transistors

Charan

Muralidharan

Raghavan

et al. 2022

Physica Status Solidi (a)

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Herein, InAlN/GaN‐on‐Si high‐electron‐mobility transistors (HEMTs) with an fT–LG product of 20.2 GHz–μm are demonstrated. The device with a gate length of 200 nm and a source–drain spacing of 900 nm exhibits a peak transconductance of 543 mS mm−1, an ION/IOFF ratio of ≈107, a maximum on‐current of 2.4 A mm−1, and an on‐resistance of 1.07 Ω mm. Small‐signal characteristics show a unity current gain cutoff frequency of 101 GHz. Delay time analysis is performed to evaluate various delay components and their contribution to the small‐signal performance of the device. An effective electron velocity of 1.56 × 107 cm s−1 is estimated in these devices, which minimizes the intrinsic delay of the transistor. The factors limiting the fT–LG product in deeply scaled devices are discussed using the delay analysis.

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“…The device presents a maximum drain current (Id, max) of 2.8 A/mm, a peak extrinsic transconductance (gm) of 0.66 S/mm, and a current/power gain cutoff frequency (fT/fmax) of 250/204 GHz. H. Xie et al reported that a record fT of 310 GHz was achieved on a InAlN/GaN HEMT on Si with a 40-nm gate length [6]. P. Cui et al demonstrated an 80-nm-gate-length InAlN/GaN HEMT on Si with a record high on/off current (Ion/Ioff) ratio of 1.58 × 10 6 , a steep subthreshold swing (SS) of 65 mV/dec, and a fT of 200 GHz, resulting in a record high fT × Lg = 16 GHz•µm [7].…”

Section: Introductionmentioning

confidence: 99%

Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

Cui

Zeng

2022

Preprint

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Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz∙V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

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Deeply-scaled GaN-on-Si high electron mobility transistors with record cut-off frequency f _T of 310 GHz

Cited by 29 publications

References 32 publications

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

20.2 GHz‐µmf_T–L_Gin InAlN/GaN‐on‐Si High Electron Mobility Transistors

Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

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Deeply-scaled GaN-on-Si high electron mobility transistors with record cut-off frequency f T of 310 GHz

Cited by 29 publications

References 32 publications

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

Development of GaN HEMTs Fabricated on Silicon, Silicon-on-Insulator, and Engineered Substrates and the Heterogeneous Integration

20.2 GHz‐µmfT–LGin InAlN/GaN‐on‐Si High Electron Mobility Transistors

Scaling Behavior of InAlN/GaN HEMTs on Silicon for RF Applications

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Deeply-scaled GaN-on-Si high electron mobility transistors with record cut-off frequency f _T of 310 GHz

20.2 GHz‐µmf_T–L_Gin InAlN/GaN‐on‐Si High Electron Mobility Transistors