DeepBurning-GL

Liang, Shengwen; Liu, Cheng; Wang, Ying; Li, Huawei; Li, Xiaowei

doi:10.1145/3400302.3415645

Cited by 21 publications

(9 citation statements)

References 29 publications

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“…The measured T LoC of GraphAGILE is the time duration from the time the GNN model (defined using PyG API) and the input graph are provided, to the time the input graph is processed and the instruction sequence is generated by the compiler. For the design automation frameworks [6], [12], T LoC includes hardware meta compilation, hardware synthesis, Place&Route, and FPGA reconfiguration.…”

Section: Implementation and Settingsmentioning

confidence: 99%

“…The reason is that data partitioning is the most time-consuming operation with complexity O( V + E ). The design automation frameworks (e.g., DeepBurning-GL [12]) undergo hours of overhead to perform hardware synthesis and Place&Route. Thus, the proposed software compiler is fast and light-weight.…”

Section: Execution Time and Size Of Binary Filementioning

confidence: 99%

“…We compare with state-of-the-art accelerators: HyGCN [5], AWB-GCN [11], DeepBuring-GL [12] and BoostGCN [6].…”

Section: Comparison With the State-of-the-art Acceleratorsmentioning

confidence: 99%

“…For example, due to the large GPU global memory footprint for storing the intermediate results, programs written with PyG spend 55%-99% [5] time executing the sparse computations of GNN inference. Many GNN accelerators [5], [6], [7], [10], [11], [12], [13], [14], [15] have been proposed to overcome the inefficiency of CPUs and GPUs. Previous works either directly design accelerators for specific GNN models [10], [11] or develop design automation frameworks [6], [12], [13] to generate FPGA accelerators for a specific GNN model and an input graph.…”

Section: Introductionmentioning

confidence: 99%

“…Many GNN accelerators [5], [6], [7], [10], [11], [12], [13], [14], [15] have been proposed to overcome the inefficiency of CPUs and GPUs. Previous works either directly design accelerators for specific GNN models [10], [11] or develop design automation frameworks [6], [12], [13] to generate FPGA accelerators for a specific GNN model and an input graph. However, the design automation frameworks need to regenerate optimized hardware design if the structure of the GNN model or the topology of the input graph changes.…”

Section: Introductionmentioning

confidence: 99%

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GraphAGILE: An FPGA-based Overlay Accelerator for Low-latency GNN Inference

Zhang¹,

Zeng²,

Prasanna³

2023

Preprint

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This paper presents GraphAGILE, a domain-specific FPGA-based overlay accelerator for graph neural network (GNN) inference. GraphAGILE consists of (1) a novel unified architecture design with an instruction set, and (2) a compiler built upon the instruction set that can quickly generate optimized code. Due to the proposed instruction set architecture (ISA) and the compiler, GraphAGILE does not require any FPGA reconfiguration when performing inference on various GNN models and input graphs. For the architecture design, we propose a novel hardware module named Adaptive Computation Kernel (ACK), that can execute various computation kernels of GNNs, including general matrix multiplication (GEMM), sparse-dense matrix multiplication (SpDMM) and sampled dense-dense matrix multiplication (SDDMM). The compiler takes the specifications of a GNN model and the graph meta data (e.g., the number of vertices and edges) as input, and generates a sequence of instructions for inference execution. We develop the following compiler optimizations to reduce inference latency: (1) computation order optimization that automatically reorders the computation graph to reduce the total computation complexity, (2) layer fusion that merges adjacent layers to reduce data communication volume, (3) data partitioning with a partition-centric execution scheme that partitions the input graph to fit the available on-chip memory of FPGA, (4) kernel mapping that automatically selects execution mode for ACK, and performs task scheduling to overlap computation with data communication and achieves dynamic load balance. We implement GraphAGILE on a state-of-the-art FPGA platform, Xilinx Alveo U250. GraphAGILE can execute widely used GNN models, including GCN, GAT, GIN, GraphSAGE, SGC and other GNN models supported by GraphGym. Experimental results show that GraphAGILE achieves up to 47.1× (3.9×) reduction in end-to-end latency, including the latency of compilation and hardware execution, compared with the state-of-the-art implementations on CPU (GPU), and achieves up to 2.9× reduction in hardware execution latency compared with the state-of-the-art FPGA accelerators.

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Section: Implementation and Settingsmentioning

confidence: 99%

Section: Execution Time and Size Of Binary Filementioning

confidence: 99%

“…We compare with state-of-the-art accelerators: HyGCN [5], AWB-GCN [11], DeepBuring-GL [12] and BoostGCN [6].…”

Section: Comparison With the State-of-the-art Acceleratorsmentioning

confidence: 99%