Deep Sub-Micron CMOS (/spl mu/m CMOS: RT or Cryo-, 0.25/spl mu/m pMOS: Buried or Surface Channel?)

Taking Silicon to the Limit: Challenges and Opportunities

“…The work function of a fully silicided (FUSI) gate material can be adjusted via doping of the precursor Si gate material. 37 Researchers have recently demonstrated that Φ M for a FUSI NiSi gate on SiO 2 gate dielectric can be tuned over a significant range 38 (from 4.5 eV to 4.9 eV, for dopant implant doses up to ~3 × 10 15 cm -2 39 ) and have successfully applied this gate technology to fabricate CMOS FinFETs with nearly symmetrical V T 's. 40 The NiSi is formed at low temperature ≤500°C) and cannot withstand high annealing temperature; hence, the silicidation must be the last thermal processing step in the transistor fabrication process.…”

Silicon: Into the Nano Era (Spring 2005)

“…The work function of a fully si'licided (FUSI) gate material can be adjusted via doping of the precursor Si gate material. 37 Researchers have recently demonstrated that <PM for a FUSI NiSi gate on Si0 2 gate dielectric can be tuned over a significant range 38 (from 4.5 eV to 4.9 eV, for dopant implant doses up to -3 x 1015 cm-239 ) and have successfully applied this ga~e technology to fabricate CMOS FinFETs with nearly symmetrical V T 's. 40 The NiSi is formed at low temperature s500°C) and cannot withstand high annealing temperature; hence, the silicidation must be the last thermal processing step in the transistor fabrication process.…”