Decoupled software pipelining creates parallelization opportunities

Huang, Jialu; Raman, Arun; Jablin, Thomas B.; Zhang, Yun; Hung, Tzu-Han; August, David I.

doi:10.1145/1772954.1772973

Cited by 48 publications

(41 citation statements)

References 25 publications

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“…Clairvoyance builds upon techniques such as software pipelining [9], [11], program slicing [12], and decoupled access-execute [13], [14], [15] and generates code that exhibits improved memory-level parallelism (MLP) and instruction-level parallelism (ILP). For this, Clairvoyance prioritizes the execution of critical instructions, namely loads, and identifies independent instructions that can be interleaved between loads and their uses.…”

Section: The Clairvoyance Compilermentioning

confidence: 99%

Static Instruction Scheduling for High Performance on Limited Hardware

Tran

Carlson

Koukos

et al. 2018

IEEE Trans. Comput.

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Abstract-Complex out-of-order (OoO) processors have been designed to overcome the restrictions of outstanding long-latency misses at the cost of increased energy consumption. Simple, limited OoO processors are a compromise in terms of energy consumption and performance, as they have fewer hardware resources to tolerate the penalties of long-latency loads. In worst case, these loads may stall the processor entirely. We present Clairvoyance, a compiler based technique that generates code able to hide memory latency and better utilize simple OoO processors. By clustering loads found across basic block boundaries, Clairvoyance overlaps the outstanding latencies to increases memory-level parallelism. We show that these simple OoO processors, equipped with the appropriate compiler support, can effectively hide long-latency loads and achieve performance improvements for memory-bound applications. To this end, Clairvoyance tackles (i) statically unknown dependencies, (ii) insufficient independent instructions, and (iii) register pressure. Clairvoyance achieves a geomean execution time improvement of 14% for memory-bound applications, on top of standard O3 optimizations, while maintaining compute-bound applications' high-performance.

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Section: The Clairvoyance Compilermentioning

confidence: 99%

Static Instruction Scheduling for High Performance on Limited Hardware

Tran

Carlson

Koukos

et al. 2018

IEEE Trans. Comput.

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show abstract

“…Clairvoyance builds upon techniques such as software pipelining [9,10], program slicing [11], and decoupled access-execute [12][13][14] and generates code that exhibits improved memory-level parallelism (MLP) and instructionlevel parallelism (ILP). For this, Clairvoyance prioritizes the execution of critical instructions, namely loads, and identifies independent instructions that can be interleaved between loads and their uses.…”

Section: The Clairvoyance Compilermentioning

confidence: 99%

Clairvoyance: Look-ahead compile-time scheduling

Tran

Carlson

Koukos

et al. 2017

2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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To enhance the performance of memory-bound applications, hardware designs have been developed to hide memory latency, such as the out-of-order (OoO) execution engine, at the price of increased energy consumption. Contemporary processor cores span a wide range of performance and energy efficiency options: from fast and power-hungry OoO processors to efficient, but slower in-order processors. The more memory-bound an application is, the more aggressive the OoO execution engine has to be to hide memory latency.This proposal targets the middle ground, as seen in a simple OoO core, which strikes a good balance between performance and energy efficiency and currently dominates the market for mobile, hand-held devices and high-end embedded systems. We show that these simple, more energy-efficient OoO cores, equipped with the appropriate compile-time support, considerably boost the performance of single-threaded execution and reach new levels of performance for memorybound applications.Clairvoyance generates code that is able to hide memory latency and better utilize the OoO engine, thus delivering higher performance at lower energy. To this end, Clairvoyance overcomes restrictions which yielded conventional compile-time techniques impractical: (i) statically unknown dependencies, (ii) insufficient independent instructions, and (iii) register pressure. Thus, Clairvoyance achieves a geomean execution time improvement of 7% for memory-bound applications with a conservative approach and 13% with a speculative but safe approach, on top of standard O3 optimizations, while maintaining compute-bound applications' high-performance.

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“…Dataflow graphs are standard intermediate representations within compilers, and can be mapped to cores automatically. There also exist transformations to increase the amount of time that an execution pattern can be used; Zhong et al use speculation to extract more DOALL parallelism [27], and pipeline parallelism can become an enabling transformation for other forms of parallelism [11].…”

Section: Related Workmentioning

confidence: 99%

Exploiting Tightly-Coupled Cores

Bates

Bradbury

Koltes

et al. 2014

J Sign Process Syst

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The individual processors of a chipmultiprocessor traditionally have rigid boundaries. Inter-core communication is only possible via memory, and control over a core's resources is localised. The specialisation necessary to meet today's challenging energy targets is typically provided through the provision of a range of processor types and accelerators. An alternative approach is to permit specialisation by tailoring the way a large number of homogeneous cores are used. The approach here is to relax processor boundaries, create a richer mix of intercore communication mechanisms and provide finer-grain control over, and access to, the resources of each core. We evaluate one such design, called Loki, that aims to support specialisation in software on a homogeneous many-core architecture. We focus on the design of a single 8-core tile, conceived as the building block for a larger many-core system. We explore the tile's ability to support a range of parallelisation opportunities and detail the control and communication mechanisms needed to exploit each core's resources in a flexible manner. Performance and a detailed

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Decoupled software pipelining creates parallelization opportunities

Cited by 48 publications

References 25 publications

Static Instruction Scheduling for High Performance on Limited Hardware

Static Instruction Scheduling for High Performance on Limited Hardware

Clairvoyance: Look-ahead compile-time scheduling

Exploiting Tightly-Coupled Cores

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