Decoder-based multi-context interconnect architecture

Lodi, Andrea; Ciccarelli, L.; Cappelli, Andrea; Carnpi, F.; Toma, M.

doi:10.1109/isvlsi.2003.1183478

Cited by 2 publications

(8 citation statements)

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“…Switch occurs within one or two clock cycles [97]. One more significant problem that arises from the implementation of additional configuration memory plane on an FPGA device is the increased power consumption [68,18]. This is due to the fact that multiple memory cells are drawing static power but are not providing any functionality at that moment.…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

“…There were several different approaches to mitigate the problem of power consumption and the area increase by using Floating-Gate-MOS Functional Pass-Gate [40], as well as Decoder-Based Multi-context interconnect structure [68]. However, these solutions are still limited to only few possible contexts and are appropriate only for applications with limited configuration variations.…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

“…Therefore, context switching is not cost-efficient in the solutions that are used for industrial applications and where cost is critical. The external configuration controller of the multi-context FPGA is not discussed in detail by [97,68,18]. However, it is assumed to be a conventional configuration controller used in most of the FPGA devices.…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

“…On the other hand, the internal configuration controller can be considered as an array of multiplexers that perform a selection of the configuration IP-core from the available SRAM cells. Configuration memory management also was not addressed in the [97,68,18] papers regarding the multi-context FPGAs, and therefore, cannot be evaluated in detail in this overview.…”

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

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The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Kirischian¹

2021

Preprint

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The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

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Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

Section: Context Switch Fpga Architecturesmentioning

confidence: 99%

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