IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.
DOI: 10.1109/isvlsi.2003.1183478
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Decoder-based multi-context interconnect architecture

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Cited by 2 publications
(8 citation statements)
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“…Switch occurs within one or two clock cycles [97]. One more significant problem that arises from the implementation of additional configuration memory plane on an FPGA device is the increased power consumption [68,18]. This is due to the fact that multiple memory cells are drawing static power but are not providing any functionality at that moment.…”
Section: Context Switch Fpga Architecturesmentioning
confidence: 99%
See 3 more Smart Citations
“…Switch occurs within one or two clock cycles [97]. One more significant problem that arises from the implementation of additional configuration memory plane on an FPGA device is the increased power consumption [68,18]. This is due to the fact that multiple memory cells are drawing static power but are not providing any functionality at that moment.…”
Section: Context Switch Fpga Architecturesmentioning
confidence: 99%
“…There were several different approaches to mitigate the problem of power consumption and the area increase by using Floating-Gate-MOS Functional Pass-Gate [40], as well as Decoder-Based Multi-context interconnect structure [68]. However, these solutions are still limited to only few possible contexts and are appropriate only for applications with limited configuration variations.…”
Section: Context Switch Fpga Architecturesmentioning
confidence: 99%
See 2 more Smart Citations
“…Switch occurs within one or two clock cycles [97]. One more significant problem that arises from the implementation of additional configuration memory plane on an FPGA device is the increased power consumption [68,18]. This is due to the fact that multiple memory cells are drawing static power but are not providing any functionality at that moment.…”
Section: Context Switch Fpga Architecturesmentioning
confidence: 99%