Decimal Floating-Point Square Root Using Newton-Raphson Iteration

Wang, Liang-Kai; Schulte, Michael

doi:10.1109/asap.2005.29

Cited by 22 publications

(7 citation statements)

References 8 publications

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“…2) of a given integer number x. Among these methods are: the rough estimation (Ercegovac, 2007), binary search (BS) (Higginbotham, 1993) and the two most studied methods by the research community, the Newton-Raphson (NR) method (Wang & Schulte, 2005) and the digit-recurrence algorithm, which is also known as digit-by-digit calculation or digit sequential algorithm (Montuschi et al, 2007;Piñeiro et al, 2004;Samavi, Sadrabadi, & Fanian, 2008;Sutikno, 2010;Takagi, 2001;Takagi & Takagi, 2006;Torres-Jimenez et al, 2011;Xiumin, Yang, Qiang, & Shihua, 2009;Yamin & Wanming, 1997).…”

Section: Related Workmentioning

confidence: 99%

An efficient FPGA architecture for integerη^throot computation

Rangel-Valdez¹,

Barrón-Zambrano

Torres-Huitzil

et al. 2014

International Journal of Electronics

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In embedded computing, it is common to find applications such as signal processing, image processing, computer graphics or data compression that might benefit from hardware implementation for the computation of integer roots of order N ! 2. However, the scientific literature lacks architectural designs that implement such operations for different values of N, using a low amount of resources. This article presents a parameterisable field programmable gate array (FPGA) architecture for an efficient Nth root calculator that uses only adders/subtractors and N 2 location memory elements. The architecture was tested for different values of N ¼ f2; 6; 10; 14; 17g, using 64-bit number representation. The results show a consumption up to 10% of the logical resources of a Xilinx XC6SLX45-CSG324C device, depending on the value of N. The hardware implementation improved the performance of its corresponding software implementations in one order of magnitude. The architecture performance varies from several thousands to seven millions of root operations per second.

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Section: Related Workmentioning

confidence: 99%

An efficient FPGA architecture for integerη^throot computation

Rangel-Valdez¹,

Barrón-Zambrano

Torres-Huitzil

et al. 2014

International Journal of Electronics

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“…The latter generally provides a more efficient method for processors. Common methods for square-rooting include first-order algorithms (Newton-Raphson [2]), binomial expansions (Goldschmidt's [3]), or Taylor-series expansion [3].…”

Section: Introductionmentioning

confidence: 99%

“…Liang-Kai and Schulte present an optimised version of the Newton-Raphson method that approximates X −1/2 [2], using the following equation:…”

Section: Introductionmentioning

confidence: 99%

Efficient digital implementation of a multi‐precision square‐root algorithm

Beasley

Watson

Clarke

2018

IET Computers & Digital Techniques

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In high performance computing systems and signal processing, there is a basic set of mathematical functions that are essential. While addition, subtraction and multiplication are well understood, there is less literature on square-rooting, which is a particularly time-and resource-consuming function. Traditional non-restoring algorithms produce a mantissa half the length of the input mantissa, causing a loss of precision. This study presents a method for increasing the accuracy of this algorithm. It is shown to work for all IEEE-754R standard floating-point numbers. Error analysis shows a 57-fold (for half-precision) and 134e6fold improvement (for double-precision) in the normalised error, equivalent to at most 1 Units of Least Precision. Resource and performance optimised variants are analysed and their throughput analysed. On an Intel Stratix V device, performance optimised implementations achieve a throughput of 717 MFLOPs. Resource optimised implementations on a low-cost device require only 127 Adaptive Logic Modules and 232 registers, with a throughput of 8.56 MFLOPs. All implementations are DSP block and memory free, saving valuable resources. The maximum throughput of the presented design is 15.5 times greater than that proposed by Pimentel et al. and two orders of magnitude greater than typical multiply-accumulate methods.

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“…For example, there are several methods, which are called estimation methods, such as Newton-Raphson method [8], Babylonian method [9] and Taylor-Series expansion mehod [10]. There are also methods called digit-by-digit calculation methods, which are more suitable for FPGA Implementation purpose.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Low-Area Square Root Calculator

Jidin

Sutikno

2015

TELKOMNIKA

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IntroductionSquare root is an arithmetic operation which is widely used in various applications such as image and audio processing, scientific computation, computer graphics and digital communications [1-2-3-4]. Recently, there are many researches which implement the square root calculator in hardware like Field Programmable Gate Array (FPGA) in order to achieve high speed computation. The main interest of implementing square root calculation in hardware is to reduce the delays present in its computation, thus producing a very fast computation.In many VLSI applications nowadays, it is vital to create designs which are not only producing correct and accurate results, but also to provide designs with very high processing speed, where the execution delay is typically in the order of a few nanoseconds or even faster, like in the case of a computer graphic applications. However, in order to achieve the best performance from the system, certain criterias like the power consumption and the resources utilization need to be sacrificed.For instance, the computation speed in hardware can be increased by introducing techniques such as pipelining and parallel computing [5]. The latter will certainly speed up the process, however creating multiple parallel path for the same operation will cause the increase in the number of resources (i.e. Adders, Registers) used, and in consequence, the area or the size of the design will also become bigger.This case is certainly becoming an unnecessary issue which is encountered when developing medium-speed and low-speed applications, with the sampling or operating frequency is less than 10MHz, which do not required very high speed computation with very small delays, while still need to utilize the same amount of resources and thus occupying the same area in the hardware. For example, applications like Direct Torque Control (DTC) for machines, which implemented the square root calculation in FPGA to achieve better estimation of flux and torque, only operated at a minimum sampling period of 5 µs [6]. In this case, the redundancy which had been introduced by the parallel computation can be eliminated and therefore, optimizing the resources usage.Besides, other strategies that need be considered is the algorithm to be implemented in hardware, for square root calculator. Unlike other basic mathematical operations such as addition, substraction or multiplication, it is very difficult to implement a square root calculation in

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Decimal Floating-Point Square Root Using Newton-Raphson Iteration

Cited by 22 publications

References 8 publications

An efficient FPGA architecture for integerη^throot computation

An efficient FPGA architecture for integerη^throot computation

Efficient digital implementation of a multi‐precision square‐root algorithm

FPGA Implementation of Low-Area Square Root Calculator

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Decimal Floating-Point Square Root Using Newton-Raphson Iteration

Cited by 22 publications

References 8 publications

An efficient FPGA architecture for integerηthroot computation

An efficient FPGA architecture for integerηthroot computation

Efficient digital implementation of a multi‐precision square‐root algorithm

FPGA Implementation of Low-Area Square Root Calculator

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An efficient FPGA architecture for integerη^throot computation

An efficient FPGA architecture for integerη^throot computation