Debugging with dominance: On-the-fly RTL debug solution implications

Abstract

Design debugging has become a resource-intensive bottleneck in modern VLSI CAD flows, consuming as much as 60% of the total verification effort. With typical design sizes exceeding the half-million synthesized gates mark, the growing number of blocks to be examined dramatically slows down the debugging process. The aim of this work is to prune the number of debugging iterations for finding all potential bugs, without affecting the debugging resolution. This is achieved by using structural dominance relationships between circuit components. More specifically, an iterative fixpoint algorithm is presented for finding dominance relationships between multiple-output blocks of the design. These relationships are then leveraged for the early discovery of potential bugs, along with their corrections, resulting in significant debugging speed-ups. Extensive experiments on real industrial designs show that 66% of solutions are discovered early due to dominator implications. This results in consistent performance gains in all cases and a 1.7x overall speed-up for finding all potential bugs, demonstrating the robustness and practicality of the proposed approach.

Non-solution implications using reverse domination in a modern SAT-based debugging environment

“…An extensive set of experiments on real industrial designs demonstrates that performing both solution and non-solution implications results in an average speedup of 1.7x in SAT solving time over performing only solution implications [12]. These results demonstrate the effectiveness and practicality of our contributions.…”

“…The authors of [12] discuss why existing methods for computing so-called single and multiple-vertex dominators are not applicable in a design debugging setting, and present a fixpoint algorithm for computing the block dominance relation D. The run-time of their algorithm is O(c · |B| · |E|), where |B| is the number of blocks, |E| is the number of edges in C and c is called the loop-connectedness of C.…”

“…In the following section, we present a branching heuristic which enables the SAT solver to find original non-solutions much faster, leading to earlier non-solution implications. Clearly, the reverse block dominance relation D −1 is completely determined by D, which can be computed using the algorithm in [12]. The set D −1 (bj) = {bi|biD −1 bj} consists of reverse dominators of bj, i.e., the blocks that bj dominates.…”

“…An all-solution SAT solver returns when a solution is found, making it possible to imply its dominating solutions [12] without modifying the SAT solver, add them to Debug using blocking clauses and continue solving. However, the SAT solver usually does not learn non-solution blocks until the end of the solving process.…”

“…A block a is said to dominate another block b if every path from every node in b to a primary output passes through a node in a. Dominators have been used to optimize various CAD tasks, e.g., test pattern generation and verification [9]- [11]. Recently, dominance between circuit blocks has been successfully used in an automated RTL debugger [12] to reduce the number of SAT solver calls by introducing the concept of solution implications.…”