Debugging the data plane with anteater

Mai, Haohui; Khurshid, Ahmed; Agarwal, Rachit; Caesar, Matthew; Godfrey, P. Brighten; King, Samuel T.

doi:10.1145/2018436.2018470

Cited by 244 publications

(191 citation statements)

References 32 publications

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“…The investigation of solutions for data plane verification was motivated by the complexity of network data planes and the difficulty in diagnosing problems (MAI et al, 2011). These solutions provide tools that generally translate a data plane configuration to a model, upon which different techniques are used to prove that it satisfies a set of properties related to a given network policy.…”

Section: Data Plane Verificationmentioning

confidence: 99%

“…These solutions provide tools that generally translate a data plane configuration to a model, upon which different techniques are used to prove that it satisfies a set of properties related to a given network policy. Examples of this approach include (MAI et al, 2011), (SON et al, 2013, (LOPES et al, 2015), and (LOPES et al, 2016). Different types of properties can be proved depending on the verification tool.…”

Section: Data Plane Verificationmentioning

confidence: 99%

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Uncovering Bugs in P4 Programs with Assertion-based Verification

Freire

Neves

Leal

et al. 2018

Proceedings of the Symposium on SDN Research

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Section: Data Plane Verificationmentioning

confidence: 99%

Section: Data Plane Verificationmentioning

confidence: 99%

Uncovering Bugs in P4 Programs with Assertion-based Verification

Freire

Neves

Leal

et al. 2018

Proceedings of the Symposium on SDN Research

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“…The tool NICE works in control plane similarly in the data plane there is another offline tool that can be used namely Anteater [5]. Anteater gathers the network topology and forwarding information bases (FIBs) of devices, and describes them as boolean functions.…”

Section: Offline Tools Supporting Automatic Test Packet Generationmentioning

confidence: 99%

“…Third action is that, Anteater interprets both the FIBs and invariants into examples of SAT, which are resolved by SAT solver. Lastly, if the results from the SAT solver show that the provided invariants are violated, Anteater will obtain a counterexample to support recognition [5].…”

Section: Fig 2:no Bugs In Controller Execution (Nice)mentioning

confidence: 99%

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A Capacious Scrutiny on Automatic Test Packet Generation

SaumitC¹,

Kulkarni²

2015

IJCA

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These days networks are not getting any smaller, they are increasing in size and it is becoming tedious job for network administrators to debug the network, since they rely on traditional tools such as ping and traceroute for this job. This paper puts forward an automated and systematic approach to test and debug a network called Automatic Test Packet Generation (ATPG). ATPG produces a model which is not dependent on devices after reading configuration from routers. The model is used to generate minimum number of test packets to cover every link in a network and each rule in network. ATPG is capable of investigating both functional and performance problems. Test packets are sent at regular intervals and separate technique is used to localize faults. The working of few offline tools which automatically generate test packets are also given, but ATPG goes beyond the earlier work in static checking (Checking liveness and fault localization). General TermsHeader space analysis, Test packet generation algorithm, Fault localization algorithm.

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Modeling and verifying SDN under Multi‐controller architectures using CSP

Xiao

Zhu

Xiang

et al. 2019

Concurrency and Computation

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Software Defined Networking (SDN) with multiple controllers draws more attention for the increasing scale of the network. Multi-controller architectures can handle what SDN with single controller is not able to address. In order to understand what these architectures can accomplish and face precisely, we analyze them with formal methods. In this paper, we apply Communicating Sequential Processes (CSP) to model the routing service of SDN under multi-controller architectures, in particular the HyperFlow architecture and the Kandoo architecture based on OpenFlow protocol. By using model checker Process Analysis Toolkit (PAT), we verify that the models satisfy three properties, namely deadlock freeness, consistency, and fault tolerance. In addition, for studying the security of those models, some extension is added. We find that the extended models are capable of coping with Denial of Service and may suffer from Information Disclosure. Moreover, a fake path and a tampered message could be present in SDN.

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Debugging the data plane with anteater

Cited by 244 publications

References 32 publications

Uncovering Bugs in P4 Programs with Assertion-based Verification

Uncovering Bugs in P4 Programs with Assertion-based Verification

A Capacious Scrutiny on Automatic Test Packet Generation

Modeling and verifying SDN under Multi‐controller architectures using CSP

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