Debugging methodology and timing analysis in CDC solution

Matsuda, Akitoshi; Zhang, Jin

doi:10.1109/asicon.2011.6157197

Cited by 2 publications

(2 citation statements)

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“…It is not uncommon for a modern digital system to use multiple clocks [33], in which data are moved from one clock domain to another and memories are connected to different clock domains. Moving from one clock domain to another requires the use of safe clock domain crossing domains -which in themselves are a large research field [24,7,28,32] -however they require using up yet more valuable resources. Typically In addition to the increase in resources required for crossing clock domains, multi-clock systems lack determinism which causes problems for the verification process.…”

Section: Clock Domain Crossingmentioning

confidence: 99%

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A distributed memory, local configuration technique for re-configurable logic designs

Beasley¹

2020

Preprint

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The use and location of memory in integrated circuits plays a key factor in their performance. Memory requires large physical area, access times limit overall system performance and connectivity can result in large fan-out. Modern FPGA systems and ASICs contain an area of memory used to set the operation of the device from a series of commands set by a host. Implementing these settings registers requires a level of care otherwise the resulting implementation can result in a number of large fan-out nets that consume valuable resources complicating the placement of timing critical pathways. This paper presents an architecture for implementing and programming these settings registers in a distributed method across an FPGA and how the presented architecture works in both clock-domain crossing and dynamic partial re-configuration applications. The design is compared to that of a 'global' settings register architecture. We implement the architectures using Intel FPGAs Quartus Prime software targeting an Intel FPGA Cyclone V. It is shown that the distributed memory architecture has a smaller resource cost (as small as 25% of the ALMs and 20% of the registers) compared to the global memory architectures.

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Section: Clock Domain Crossingmentioning

confidence: 99%

“…Rectifying the non-deterministic nature of such systems and providing verification techniques (both stand-alone and built-in) is a rich source of research [37,23]. Additionally, frameworks for performing timing analyses and signal integrity in a CDC application [28,32] have been proposed.…”

Section: Clock Domain Crossingmentioning

confidence: 99%