Dealing with inductance in high-speed chip design

Abstract

Inductance effects in on-chip interconnects have become significant for specific cases such as clock distributions and other highly optimized networks [1,2]. Designers and CAD tool developers are searching for ways to deal with these effects.Unfortunately, accurate on-chip inductance extraction and simulation in the general case are much more difficult than capacitance extraction. In addition, even if ideal extraction tools existed, most chip designers have little experience designing with lossy transmission lines. This tutorial will attempt to demystify on-chip inductance through the discussion of several illustrative on-chip examples analyzed using full-wave extraction and simulation methods. A specialized PEEC (Partial Element Equivalent Circuit) method tailored for chip applications was used for most cases. Effects such as overshoot, reflections, frequency dependent effective resistance and inductance will be Illustrated using animated visualizations of our full-wave simulations. Simple examples of design techniques to avoid, mitigate, and even take advantage of on-chip inductance effects will be described.

A 3Gb/s/wire global on-chip bus with near velocity-of-light latency

“…The return path structure or changes in termination of nearby wires affects return current distribution and thus inductance and effective resistance. This in turn affects propagation delay [10]. Therefore, to provide a well-defined current return path is a relevant step in the design strategy to realize well-behaved velocity-of-light limited interconnects.…”

On the impact of on-chip inductance on signal nets under the influence of power grid noise

“…W ITH THE continuing push for performance, higher on-chip signal slew rate coupled with longer on-chip interconnects have made it necessary to include on-chip inductance into the delay and noise analysis of the on-chip interconnects [2], [4], [9], [5], [6]. The deficiencies of representing long interconnects with RC-elements in multi-gigahertz (GHz) designs are illustrated in [7] and new design methodologies are needed to deal with increasing impact of on-chip inductance.…”

“…The deficiencies of representing long interconnects with RC-elements in multi-gigahertz (GHz) designs are illustrated in [7] and new design methodologies are needed to deal with increasing impact of on-chip inductance. It has been well recognized that the impact of on-chip inductance on clock nets is significant [4], [10], [11]. This is mainly due to the fact that clock nets are often made relatively wider compared to signal nets to reduce clock signal distribution delay.…”

“…In fact, the issue of extracting on-chip inductance was first discussed in 1972 [1] by Ruehli. Deutsch et al [3] analyzed the inductive effects on interconnects with line width Manuscript ranging from 0.45 to 52 m and derived a set of conditions for when on-chip interconnects must be treated as transmission lines. Recently, Restle et al [4] asserted that on-chip inductive effects cannot be ignored for clock nets nor can a growing number of other cases involving long low-resistance wires. However, no quantitative assessment has been performed for " the growing number of long wires" across chips.…”

Impact of on-chip inductance when transitioning from Al to Cu based technology

“…al. [4] asserted that on-chip inductive effects cannot be ignored for clock nets nor can a growing number of other cases involving long low-resistance wires. However, no quantitative assessment has been performed for "the growing number of long wires" across chips.…”