Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations

Mouthaan, A.J.; Salm, Cora; Lunenborg, M.M.; Wolf, Marilyn; Kuper, F.G.

doi:10.1016/s0026-2714(99)00252-8

Cited by 13 publications

(2 citation statements)

References 21 publications

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“…They have advantages over vertical DMOS devices in that the drift region can be easily optimized for different operating voltage requirements, but because of the high voltages applied to these NLDMOS hot carrier (HC) degradation is a real reliability concern [10][11][12][13][14][15][16][17][18][19]. A key process step in the forming the NLDMOS devices is the drain drift (NDrift) implant.…”

Section: Introductionmentioning

confidence: 99%

Substrate Current Independent Hot Carrier Degradation in NLDMOS Devices

Brisbin

Lindorfer

Chaparala

2006

2006 IEEE International Reliability Physics Symposium Proceedings

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Automotive and telecom applications often require voltages in the 20-30V range. These circuits combine high performance CMOS with a high voltage MOS transistor. A possible choice for the high voltage device is an n-channel lateral DMOS transistor (NLDMOS). An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet breakdown voltage and hot carrier reliability requirements. This paper focuses on understanding anomalous hot carrier results obtained from an NLDMOS transistor whose drain drift implant dose was varied. [

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Section: Introductionmentioning

confidence: 99%

Substrate Current Independent Hot Carrier Degradation in NLDMOS Devices

Brisbin

Lindorfer

Chaparala

2006

2006 IEEE International Reliability Physics Symposium Proceedings

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“…Because of the high drain voltages and currents used in these applications LDMOS hot carrier (HC) degradation is a real reliability concern [7][8][9][10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability

Brisbin

Lindorfer

Chaparala

2006

2006 IEEE International Integrated Reliability Workshop Final Report

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Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices.

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