Dead-time optimization for SiC based voltage source converters using online condition monitoring

Dyer, Jacob; Zhang, Zheyu; Wang, Fred; Costinett, Daniel; Tolbert, Leon M.; Blalock, Benjamin J.

doi:10.1109/wipda.2017.8170495

Cited by 17 publications

(4 citation statements)

References 9 publications

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“…A dead-time optimization technique for a two-level voltage source converter using turn-off transition monitoring is proposed in [62]. By tracking the change of the load on-line, the method can adaptively calculate the optimum width of the inductor current zero-crossing region to eliminate the dead-time effect of the zero-crossing region and the non-zero-crossing region, respectively.…”

Section: Adaptive Dead-time Compensation Methodsmentioning

confidence: 99%

Control Strategies of Mitigating Dead-time Effect on Power Converters: An Overview

Yang

Zhou

et al. 2019

Electronics

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To prevent short-circuits between the upper and lower switches of power converters from over-current protection, the dead time is mandatory in the switching gating signal for voltage source converters. However, this results in many negative effects on system operations, such as output voltage and current distortions (e.g., increased level of fifth and seventh harmonics), zero-current-clamping phenomenon, and output fundamental-frequency voltage reduction. Many solutions have been presented to cope with this problem. First, the dead-time effect is analyzed by taking into account factors such as the zero-clamping phenomenon, voltage drops on diodes and transistors, and the parameters of inverter loads, as well as the parasitic nature of semiconductor switches. Second, the state-of-the-art dead-time compensation algorithms are presented in this paper. Third, the advantages and disadvantages of existing algorithms are discussed, together with the future trends of dead-time compensation algorithms. This article provides a complete scenario of dead-time compensation with control strategies for voltage source converters for researchers to identify suitable solutions based on demand and application.

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Section: Adaptive Dead-time Compensation Methodsmentioning

confidence: 99%

Control Strategies of Mitigating Dead-time Effect on Power Converters: An Overview

Yang

Zhou

et al. 2019

Electronics

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“…The forward conduction voltage V F of the SHG-DTMOS at a current density of 100 A/cm 2 is 1.88 V, which is approximately 34% smaller than the 2.88 V of the Con-DTMOS and the SG-DTMOS, respectively. This low forward conduction voltage results in a lower dead-time energy loss [28]. Figure 6a,b show the electron and hole current distributions of each device at the forward voltage.…”

Section: Body Diode and Switching Characteristicsmentioning

confidence: 99%

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Cheon

Kim

2021

Materials

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In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

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“…The dead-time refers to the intentional delay between turning off one IGBT in a phase leg and turning on its complementary IGBT. However, such a blanking period can affect the reliability, power quality, and losses of the system [11][12][13][14][15][16][17][18]. Furthermore, if issues associated with dead-time are not addressed appropriately, it may result in voltage distortions [11].…”

Section: Introductionmentioning

confidence: 99%

Dead-Time Effect in Inverters on Wireless Power Transfer

Rajs,

Herceg,

Despotović

et al. 2024

Electronics

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This paper presents a comprehensive analysis of the dead-time effects in wireless power transfer systems based on LCC-S topology. In these systems operating at high frequencies, the ratio of dead-time versus the operating period becomes critical, and the dead-time issue can cause certain problems regarding power quality, efficiency, and output voltage ripple. The impact of input quantities such as voltage and switching frequency on the efficiency and output power of the LCC-S-tuned WPT system was also investigated. The optimal combination of these parameters used to achieve the maximum efficiency for a target output power and to set the appropriate value of the dead time were determined by running multiple simulations using the MATLAB R2023b software platform. It was also shown that the output voltage remained unchanged with and without a load and up to 1200 ns of dead-time, which provides a simple implementation of the corresponding mathematical model. In the recommended interval of 600–1500 ns, the influence of the dead-time on the value of the output voltage amplitude is less than 10%. The validity of the proposed method was confirmed through the implementation of the experimental prototype, a 5 kW wireless power transmission system, and the obtained results were in accordance with the simulation results.

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Dead-time optimization for SiC based voltage source converters using online condition monitoring

Cited by 17 publications

References 9 publications

Control Strategies of Mitigating Dead-time Effect on Power Converters: An Overview

Control Strategies of Mitigating Dead-time Effect on Power Converters: An Overview

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Dead-Time Effect in Inverters on Wireless Power Transfer

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