De-RISC: the First RISC-V Space-Grade Platform for Safety-Critical Systems

Abstract

The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, verifiability and validation requirements since spacecraft for deep space missions are exposed to a harsh environment. Systems must undergo screening and tests against standards for electronic components and software. Unfortunately, currently available space-grade processor components do not meet requirements related to safety that are becoming increasingly important in space applications.This paper presents the De-RISC platform, consisting of Cobham Gaisler's RISC-V based SoC, and fentISS' XtratuM Next Generation hypervisor. The platform implements the open RISC-V Instruction Set Architecture, and leverages space SoC IP by Cobham Gaisler, space hypervisor technology by fentISS, multicore interference management solutions by the Barcelona Supercomputing Center, and end user experience and requirement guidance by Thales Research and Technology. At its current state, the platform is already complete and integrated, and starting its validation phase prior to reaching commercial maturity by early 2022. In this paper, we provide details of the platform and some preliminary evidence of its operation. 1) It builds upon a NOEL-V based MPSoC by Cobham Gaisler, delivering competitive performance, incorporating appropriate reliability measures for its use in space, and implementing the RISC-V ISA to reduce to a minimum export restrictions.

SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores

“…SafeDM has been implemented and evaluated in a commercial MultiProcessor System on Chip (MPSoC) used in the space industry, and developed by Cobham Gaisler [34], which builds upon NOEL-V cores. The NOEL-V based MPSoC consists of The main bus for communication is a 128 bit-wide Advanced High-performance Bus (AHB).…”

A Survey of Virtualization Technologies: Towards a New Taxonomic Proposal

“…• Dynamic Binary Translation implies that the Type I Hypervisor catches and inspects the code of each guest OS request to convert it into a proper request towards the underlying hardware, e.g., VMware ESX/ESXi (Z. Li, 2021;VMware, 2022) and XtratuM (Wessman et al, 2021;Xtratum, 2022) .…”

SafeX: Open Source Hardware and Software Components for Safety-Critical Systems

“…SafeX components have no specific constraint to be integrated on a wide variety of microprocessor architectures. However, they have already been integrated in an SoC like the one illustrated in Figure 2, which shows the main architecture used in H2020 De-RISC [15] and H2020 SELENE [8]. As shown, the microprocessor includes some cores connected through a bus.…”