DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

Abstract

In this paper, a C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effect of pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I on ), on/off current ratio (I on /I off ), subthreshold swing (SS), transconductance (g m ), cut-off frequency (f T ), and gain-bandwidth product (GBP) are investigated. The optimized CSP-TFET device exhibits excellent performance with high I on (9.98×10-4 A/μm), high I on /I off (~1011), as well as low SS (~12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.

Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

“…SiO 2 was used as the gate oxide layer with a thickness of 2 nm. Based on the team's previous work, [34] we found that increasing the T p and L p2 in the C-pocket would increase the leakage current and prevent the device from switching off, and increasing the T p would also reduce the on-state current of the device. Therefore, the T p and L p2 should not be large, and we also considered the fabrication issues.…”

“…Several solutions have been proposed to suppress ambipolar currents: using asymmetric doping, [22][23][24] gate-drain underlap, [23,25,26] gate-drain overlap, [27] heterogeneous dielectrics, [23,28,29] work function engineering, [23,30,31] recessed drains [32] and spacer engineering. [33] To solve these issues, a TFET with a C-type pocket (CSP-TFET) [34] was proposed in previous work by our team, which improved the low on-state current while further reducing the sub-threshold swing; however, the ambipolar behavior was not fully suppressed. Further work is needed to optimize the structure of the device to completely suppress the ambipolar current while ensuring that the on-state current is not affected as much as possible, thus improving the performance of the device.…”

An accurate analytical surface potential model of heterojunction tunnel FET

“…The fabricated III-V heterostructure TFET (H-TFET) with a lateral tunneling junction has demonstrated excellent performance with sub-thermal operation, reaching down to 48 mV/decade, and a high current of 10.6 µA/µm at drain-to-source bias of 0.3 V. [4] The TCAD predicted III-V H-TFET with a trench gate and InGaAs pocket structure achieves simultaneously 921 µA/µm on-current and average subthreshold swing of 4.9 mV/dec. [5] Despite significant experimental and finite-element simulation efforts, [4][5][6][7][8][9][10][11][12] an accurate analytical model of the TFET is urgent and indispensable to provide further insight into the physics of the device and to accelerate the process of device and circuit designs. Furthermore, the potential model is the cornerstone of the capacitance and current models, [13,14] which thus needs to be modeled more accurately.…”