DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-All-Around Silicon Nanowire n-MOSFETs

Sung, Wen-Li; Li, Yiming

doi:10.1109/ted.2018.2822484

Cited by 24 publications

(10 citation statements)

References 25 publications

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“…[16][17][18][19][20][21] These models have been validated through the results of nonequilibrium Green's function. 22 In addition, the simulated I D -V G curve was calibrated by experimental data. 22 In this study, we only focus on the WKF simulation because the WKF is a major fluctuation source in Si GAA NW MOSFETs.…”

Section: D Device Structures and Simulation Methodsmentioning

confidence: 99%

“…22 In addition, the simulated I D -V G curve was calibrated by experimental data. 22 In this study, we only focus on the WKF simulation because the WKF is a major fluctuation source in Si GAA NW MOSFETs. 7,8 Thus, we ignored the effects of fluctuating contact resistivity, self-heating, electrostatic coupling between channels, strains of materials, surface roughness of channels, temperature, etc.…”

Section: D Device Structures and Simulation Methodsmentioning

confidence: 99%

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Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowire n-MOSFETs

Sung

2020

Journal of Elec Materi

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In this study, we present a statistically accurate model to predict the threshold-voltage variability (rV th) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW) n-MOS-FETs with multi-channels. The statistical results indicate that the rV th decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of rV th was calculated for various MGNs, which joins the normality test with Anderson-Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of rV th. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NW n-MOSFETs with multi-channels.

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Section: D Device Structures and Simulation Methodsmentioning

confidence: 99%

Section: D Device Structures and Simulation Methodsmentioning

confidence: 99%

Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowire n-MOSFETs

Sung

2020

Journal of Elec Materi

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“…Fig. 3 shows the calibration results of our models by comparing the simulation result with other's work [30].…”

Section: B Simulation Physical Models and Calibrationmentioning

confidence: 99%

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

2020

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In this letter, a novel Core-Substrate Gate-All-Around (CSGAA) nanowire structure has been proposed, investigated and simulated systematically based on 3D numerical simulation. This new structure is characterized by a Core-Substrate directly connected to the substrate wafer or well which is formed by a bulk region inside the tubular channel. Comparisons are carried out between conventional Gate-All-Around (GAA) nanowire transistor and newly proposed CSGAA structure. This budding structure exhibits a maximum of four orders of magnitude of reduction in off-state current, high saturation current and low performance degradation. With the help of Core-Substrate, the CSGAA structure is able to maintain excellent performance despite geometric and structural variation. Its special structure is very suitable for the use of vertical Gate-All-Around nanowire structure, making it a promising candidate of future high performance and low power CMOS devices. INDEX TERMS CMOS, core-substrate gate-all-around, CSGAA, field effect transistor, GAA, nanowire.

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“…To validate our simulation, we examined the band profile along the channel by solving 3D quantum mechanical transport and non-equilibrium Green’s function models. Then, we calibrated the simulation result with measurement data of the fabricated sample [34,35]. For both the N- and P-type devices, the I D –V G characteristics of the simulated device at V D = 1/−1 V were experimentally calibrated to the measured data by fitting the mobility model parameters [18,20,34,35].…”

Section: Statistical Lwkf and Ar Simulation Techniquesmentioning

confidence: 99%

“…Then, we calibrated the simulation result with measurement data of the fabricated sample [34,35]. For both the N- and P-type devices, the I D –V G characteristics of the simulated device at V D = 1/−1 V were experimentally calibrated to the measured data by fitting the mobility model parameters [18,20,34,35]. Because the I D –V G characteristics are well-fitted between the fabrication and the simulation, this further ensures the accuracy of our statistical device and circuit simulation.…”

Section: Statistical Lwkf and Ar Simulation Techniquesmentioning

confidence: 99%

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

Chen

Chuang

et al. 2019

Materials

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In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.

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DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-All-Around Silicon Nanowire n-MOSFETs

Cited by 24 publications

References 25 publications

Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowire n-MOSFETs

Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowire n-MOSFETs

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

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