Dataflow Implementation of QR Decomposition on a Manycore

Savas, Süleyman; Raase, Sebastian; Gebrewahid, Essayas; Ul-Abdin, Zain; Nordström, Tomas

doi:10.1145/2934495.2934499

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…In this step, an important decision is the choice of NoC topology. The efficiency of the topology might change based on the domain of the applications However, for dataflow applications, we suggest a 2D mesh structure based on our experience during previous work [22,58] with the Epiphany architecture [59]. This structure provides efficient core-to-core communication for dataflow applications in terms of bandwidth and latency.…”

Section: System Integrationmentioning

confidence: 99%

“…It is also a part of the solution to the linear least squares problem and the basis of an eigenvalue algorithm (the QR algorithm). There are several different methods to perform QRD, such as the Givens Rotations, Householder and Gram-Schmidt methods [22].…”

Section: Qr Decompositionmentioning

confidence: 99%

“…We considered two case studies to evaluate the performance and area usage of the generated code. The first case study was QR decomposition (QRD), implemented using Givens Rotations method [22]. The QRD operation is used in numerous signal processing applications including massive MIMO [23].…”

Section: Introductionmentioning

confidence: 99%

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Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

2018

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The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures-and, consequently, exploration of the design space-by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4× improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5-13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of handwritten implementations.

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Section: System Integrationmentioning

confidence: 99%

Section: Qr Decompositionmentioning

confidence: 99%

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Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

2018

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“…With their technique, Savas et al [125] observe speedup between 1.3 and 4.3 over hand-written code. In [126], Savas et al compare CAL-optimized scientific applications deployed on Epiphany [1] to hand-written GNU scientific library running on a unique ARM processor and observe a x30 speedup. They further note that the development of ap-6.5.…”

Section: Related Workmentioning

confidence: 99%

Algorithms and Framework for Energy Efficient Parallel Stream Computing on Many-Core Architectures

Melot¹

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The rise of many-core processor architectures in the market answers to a constantly growing need of processing power to solve more and more challenging problems such as the ones in computing for big data. Fast computation is more and more limited by the very high power required and the management of the considerable heat produced. Many programming models compete to take profit of many-core architectures to improve both execution speed and energy consumption, each with their advantages and drawbacks. The work described in this thesis is based on the dataflow computing approach and investigates the benefits of a carefully pipelined execution of streaming applications, focusing in particular on off-and on-chip memory accesses. As case study, we implement classic and on-chip pipelined versions of mergesort for Intel SCC and Xeon. We see how the benefits of the on-chip pipelining technique are bounded by the underlying architecture, and we explore the problem of fine tuning streaming applications for many-core architectures to optimize for energy given a throughput budget. We propose a novel methodology to compute schedules optimized for energy efficiency given a fixed throughput target. We introduce Drake, derived from Schedeval, a tool that generates pipelined applications for Many-Core architectures and allows the performance testing in time or energy of their static schedule. We show that streaming applications based on Drake compete with specialized implementations and we use Schedeval to demonstrate performance differences between schedules that are otherwise considered as equivalent by a simple model. This work has been supported in parts by CUGS (the Graduate School in Computer Science, Sweden), Vetenskapsrådet, SeRC and EU FP7 EXCESS. Department of Computer and Information ScienceLinköping University SE-581 83 Linköping, Sweden Acknowledgements I would like to thank all members of PELAB for the inspiring and stimulating working environment as well as the passionate discussions around coffee or tea. In particular, my thanks to Kristian Sandahl for his efforts at maintening a strong group culture. Warm thanks to Christoph Kessler, for all fruitful discussions and ideas when my imagination came short, for his support and patience when results came late and for entrusting me with opportunities and responsibilities that taught me valuable experiences. Many thanks to Jörg Keller for sharing his ideas in details about my work, and for always carefully reviewing and challenging any hypothesis I proposed, as it repeatedly resulted in strengthening good ideas and discarding bad ones. I would like to thank all students who participated in the work, providing a precious help to progress. I am grateful to Intel for providing the Single Chip Cloud computer research prototype and their efforts to help in the numerous moments where nothing worked. Many thanks to the National Supercomputer Center (NSC) for providing powerful computing means to run my experiments, TUS for always providing a quick and precious technica...

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Estimating Stream Application Performance in Early-Stage System Design

Callanan

Gruian

2022

2022 56th Asilomar Conference on Signals, Systems, and Computers

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Dataflow Implementation of QR Decomposition on a Manycore

Cited by 5 publications

References 12 publications

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Algorithms and Framework for Energy Efficient Parallel Stream Computing on Many-Core Architectures

Estimating Stream Application Performance in Early-Stage System Design

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