Data transformations for eliminating conflict misses

Rivera, Gabriel; Tseng, Chau‐Wen

doi:10.1145/277650.277661

Cited by 173 publications

(43 citation statements)

References 21 publications

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“…Thus, in the past decades there have been many studies [9,26,27] that have analyzed the performance impact and improved the design of caches. Apart from hardware solutions, software solutions have been proposed to reduce the miss rate of the instruction cache [17] and the data cache [23]. These software optimizations are implemented in compilers [7,14,22] or using profile information [20].…”

Section: Related Workmentioning

confidence: 99%

Evaluating the impact of dynamic binary translation systems on hardware cache performance

Ruiz-Alvarez

Hazelwood

2008

2008 IEEE International Symposium on Workload Characterization

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Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previously translated instructions. The code layout in the code cache greatly differs from the code layout of the original program. This paper provides an exhaustive analysis of the performance of the instruction/trace cache and other structures of the microarchitecture while executing DBTs that focus on program instrumentation, such as DynamoRIO and Pin.We performed our evaluation along two axes. First, we directly accessed the hardware performance counters to determine actual cache miss counts. Second, we used simulation to analyze the spatial locality of the translated application. Our results show that when executing an application under the control of Pin or DynamoRIO, the icache miss counts actually increase over 2X. Surprisingly, the L2 cache and the L1 data cache show a much lower performance degradation or even break even with the native application. We also found that overall performance degradations are due to the instructions added by the DBT itself, and that these extra instructions outweigh any possible spatial locality benefits exhibited in the code cache. Our observations held regardless of the trace length, code cache size, or the presence of a hardware trace cache. These results provide a better understanding of the efficiency of current instrumentation tools and their effects on instruction/trace cache performance and other structures of the microarchitecture.

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Section: Related Workmentioning

confidence: 99%

Evaluating the impact of dynamic binary translation systems on hardware cache performance

Ruiz-Alvarez

Hazelwood

2008

2008 IEEE International Symposium on Workload Characterization

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“…Rivera and Tseng in [14] use padding to eliminate severe conflict misses. Inter-variable padding adjusts variable base addresses, while intra-variable padding modifies array dimension sizes.…”

Section: Introductionmentioning

confidence: 99%

Improving cache locality with blocked array layouts

Athanasaki

Koziris

2004

12th Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2004. Proceedings.

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Minimizing cache misses is one of the most important factors to reduce average latency for memory accesses. Tiled codes modify the instruction stream to exploit cache locality for array accesses. In this paper, we further reduce cache misses, restructuring the memory layout of multidimensional arrays, that are accessed by tiled instruction code. In our method, array elements are stored in a blocked way, exactly as they are swept by the tiled instruction stream. We present a straightforward way to easily translate multidimensional indexing of arrays into their blocked memory layout using simple binary-mask operations. Indices for such array layouts are easily calculated based on the algebra of dilated integers, similarly to morton-order indexing. Actual experimental results, using matrix multiplication and LU-decomposition on various size arrays, illustrate that execution time is greatly improved when combining tiled code with tiled array layouts and binary maskbased index translation functions. Simulations using the Simplescalar tool, verify that enhanced performance is due to the considerable reduction of total cache misses.

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“…The main difference between our work and these two studies is that we focus on an MPSoC based architecture instead of a single processor based system. Riveral and Tseng [8] discuss techniques that minimize the number of conflict misses by transforming data layouts. Their work is focused on single processor environment.…”

Section: Discussion Of Related Workmentioning

confidence: 99%

Locality-Aware Process Scheduling for Embedded MPSoCs

Kandemir

Chen

Design, Automation and Test in Europe

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Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work that targets at optimizing cache behavior are performed at hardware and compilation levels, operating system (OS) can also play major role as it sees the global access pattern information across applications. This paper proposes a cache-conscious OS process scheduling strategy based on data reuse. The proposed scheduler implements two complementary approaches. First, the processes that do not share any data between them are scheduled at different cores if it is possible to do so. Second, the processes that could not be executed at the same time (due to dependences) but share data among each other are mapped to the same processor core so that they share the cache contents. Our experimental results using this new data locality aware OS scheduling strategy are promising, and show significant improvements in task completion times.

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Data transformations for eliminating conflict misses

Cited by 173 publications

References 21 publications

Evaluating the impact of dynamic binary translation systems on hardware cache performance

Evaluating the impact of dynamic binary translation systems on hardware cache performance

Improving cache locality with blocked array layouts

Locality-Aware Process Scheduling for Embedded MPSoCs

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