Data Centric Cache Measurement on the Intel ltanium 2 Processor

Buck, Bryan; Hollingsworth, Jeffrey K.

doi:10.1109/sc.2004.21

Cited by 22 publications

(9 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Buck and Hollingsworth developed Cache Scope [7] to perform data-centric analysis using Itanium 2 event address registers (EAR). Cache Scope associates latency with data objects and functions that accessed them.…”

Section: Tools For Identifying Poor Cache Localitymentioning

confidence: 99%

“…A variety of data-centric tools currently exist; we discuss them in detail in Section 6. Some tools focus on data locality in sequential codes [25,26,7]; the others focus on NUMA problems in threaded codes [28,20]; none of them supports comprehensive analysis of all kinds of data locality problems. Moreover, existing tools work on modest numbers of cores on a single node system; none of them tackles the challenge of scaling and is applicable across a cluster with many hardware threads on each node.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A data-centric profiler for parallel programs

Liu

Mellor-Crummey

2013

Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

View full text Add to dashboard Cite

It is difficult to manually identify opportunities for enhancing data locality. To address this problem, we extended the HPCToolkit performance tools to support data-centric profiling of scalable parallel programs. Our tool uses hardware counters to directly measure memory access latency and attributes latency metrics to both variables and instructions. Different hardware counters provide insight into different aspects of data locality (or lack thereof). Unlike prior tools for data-centric analysis, our tool employs scalable measurement, analysis, and presentation methods that enable it to analyze the memory access behavior of scalable parallel programs with low runtime and space overhead. We demonstrate the utility of HPCToolkit's new data-centric analysis capabilities with case studies of five well-known benchmarks. In each benchmark, we identify performance bottlenecks caused by poor data locality and demonstrate non-trivial performance optimizations enabled by this guidance.

show abstract

Section: Tools For Identifying Poor Cache Localitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A data-centric profiler for parallel programs

Liu

Mellor-Crummey

2013

Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

View full text Add to dashboard Cite

show abstract

“…Tikir et al describe a profile-driven online page migration scheme using hardware performance counters [Mustafa M. Tikir 2004]. Buck et al use the Itanium-2 data tracing PMU support to associate load misses to source code lines and data structures in uniprocessor programs [Buck and Hollingsworth 2004]. Buck et al also compare different hardware mechanism for detecting uniprocessor memory hierarchy bottlenecks [Buck and Hollingsworth 2000b].…”

Section: Related Workmentioning

confidence: 99%

Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

Marathe

Mueller

Supinski

2006

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Application performance on high-performance shared-memory systems is often limited by sharing patterns resulting in cache-coherence bottlenecks. Current approaches to identify coherence bottlenecks incur considerable run-time overhead and do not scale.We present two novel hardware-assisted coherence-analysis techniques that reduce trace sizes by two orders of magnitude over full traces. First, hardware performance monitoring is combined with capturing stores in software to provide a lossy-trace mechanism, which is an order of magnitude faster than software-instrumentation-based full-tracing and retains accuracy. Second, selected long-latency loads are instrumented via binary rewriting, which provides even higher accuracy and control over tracing but requires additional overhead.

show abstract

“…Tikir et al describe a profile-driven online page migration scheme using hardware performance counters [24]. Buck et al use the Itanium-2 data tracing PMU support to associate load misses to source code lines and data structures in uniprocessor programs [7]. Buck et al also compare different hardware mechanism for detecting uniprocessor memory hierarchy bottlenecks [6].…”

Section: Related Workmentioning

confidence: 99%

A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks

Marathe

Mueller

Supinski

2005

Proceedings of the 19th Annual International Conference on Supercomputing

View full text Add to dashboard Cite

High-end computing increasingly relies on shared-memory multiprocessors (SMPs), such as clusters of SMPs, nodes of chipmultiprocessors (CMP) or large-scale single-system image (SSI) SMPs. In such systems, performance is often affected by the sharing pattern of data within applications and its impact on cache coherence. Sharing patterns that result in frequent invalidations followed by subsequent coherence misses create cache coherence bottlenecks with significant performance penalties. Past work on identifying coherence bottlenecks based on tracing memory accesses incurs considerable runtime overhead and does not scale well with increasing problem sizes, which makes it infeasible to use with real-world programs.In this paper, we introduce a novel low-cost, hardware-assisted approach to determine coherence bottlenecks in shared-memory OpenMP applications. We assess the merits of our approach on a contemporary SMP platform. Specifically, we assess the feasibility of lossy tracing to pin-point coherence problems in applications. We evaluate the qualitative and quantitative trade-offs between tracing overhead and accuracy of the generated coherence traffic metrics, correlated to memory access points at the program source level.Our lossy tracing mechanism closely approximates the degree of accuracy of determining coherence misses in full traces for most of the benchmarks we study while reducing run-time execution overhead and trace sizes by one to two orders of magnitude. To the best of our knowledge, this novel method significantly outperforms any of the prior approaches and, for the first time, makes cache coherence analysis feasible for long-running applications.

show abstract

Data Centric Cache Measurement on the Intel ltanium 2 Processor

Cited by 22 publications

References 18 publications

A data-centric profiler for parallel programs

A data-centric profiler for parallel programs

Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks

Contact Info

Product

Resources

About