Data and program restructuring of irregular applications for cache-coherent multiprocessor

Tomko, Karen; Abraham, Santosh G.

doi:10.1145/181181.181351

Cited by 9 publications

(2 citation statements)

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“…However, this does not address the details of reuse, nor is it generally applicable to irregular problems. To our knowledge, [11] is the only paper that applies data repartitioning explicitly for cache optimization. They determine the size of a sub-domain of the local cache, based on an analysis of the data structures and algorithms of a problem, and then use a domain decomposition scheme at run-time to reorganize data to fit into these local cache regions.…”

Section: Introductionmentioning

confidence: 99%

“…The references of an irregular program are clustered in such a way that the data referenced in each cluster fits within the processor's cache. For static irregular codes, such as sparse matrix-vector multiplication, the number of clusters and their sizes are determined statically (once during runtime), similar to [11]. For dynamic scientific applications, such as Particle-In-Cell [1] and CHARMM [2], the clusters' scopes can change.…”

Section: Introductionmentioning

confidence: 99%

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Run-time reference clustering for cache performance optimization

Kaplow

Szymański²,

Tannenbaum³

et al.

Proceedings of IEEE International Symposium on Parallel Algorithms Architecture Synthesis

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We introduce a method for improving the cache performance of irregular computations in which data are referenced through run-time defined indirection arrays. Such computations often arise in scientific problems. The presented method, called Run-Time Reference Clustering (RTRC), is a run-time analog of a compile-time blocking used for dense matrix problems. RTRC uses the data partitioning and re-mapping techniques that are a part of distributed memory multi-processor codes designed to minimize interprocessor communication. Re-mapping each set of local data decreases cache-misses the same way remapping the global data decreases off-processor references. We demonstrate the applicability and performance of the RTRC technique on several prevalent applications: Sparse Matrix-Vector Multiply, Particle-In-Cell, and CHARMMlike codes. Performance results on SPARC-20, SP-2, and T3-D processors show that single node execution performance can be improved by as much as 35%.

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Section: Introductionmentioning

confidence: 99%