DART: A Programmable Architecture for NoC Simulation on FPGAs

Wang, Danyao; Lo, Charles; Vasiljevic, Jasmina; Jerger, Natalie Enright; Steffan, J. Gregory

doi:10.1109/tc.2012.121

Cited by 26 publications

(2 citation statements)

References 17 publications

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“…for 16-core systems. Wang et al have developed their DART system based on the FPGA technology in which various optimizations are introduced [17]. They achieved from 6M to 11M cycles/sec.…”

Section: Acceleration Techniques For Icn Simulationmentioning

confidence: 99%

“…Thus, many of these FPGA-based methods employ multiplexed operations for large-scale systems that cannot be embedded in the FPGA device. For example, literature [17] reports that multiplexed implementation slows down the simulation speed at ten to twenty times, since multiplexed sub-modules make shared use of embedded RAM modules within the FPGA device. Many of FPGA-based simulators actually cover relatively small-scale systems, where undesirable performance issues are suggested for large-scale systems.…”

Section: Acceleration Techniques For Icn Simulationmentioning

confidence: 99%

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Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept

Yokota

Ootsu

Ohkawa

2019

IEICE Trans. Inf. & Syst.

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State-of-the-art parallel systems employ a huge number of computing nodes that are connected by an interconnection network. An interconnection network (ICN) plays an important role in a parallel system, since it is responsible to communication capability. In general, an ICN shows non-linear phenomena in its communication performance, most of them are caused by congestion. Thus, designing a large-scale parallel system requires sufficient discussions through repetitive simulation runs. This causes another problem in simulating large-scale systems within a reasonable cost. This paper shows a promising solution by introducing the cellular automata concept, which is originated in our prior work. Assuming 2D-torus topologies for simplification of discussion, this paper discusses fundamental design of router functions in terms of cellular automata, data structure of packets, alternative modeling of a router function, and miscellaneous optimization. The proposed models have a good affinity to GPGPU technology and, as representative speed-up results, the GPU-based simulator accelerates simulation upto about 1264 times from sequential execution on a single CPU. Furthermore, since the proposed models are applicable in the shared memory model, multithread implementation of the proposed methods achieve about 162 times speed-ups at the maximum.

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“…for 16-core systems. Wang et al have developed their DART system based on the FPGA technology in which various optimizations are introduced [17]. They achieved from 6M to 11M cycles/sec.…”

Section: Acceleration Techniques For Icn Simulationmentioning

confidence: 99%

Section: Acceleration Techniques For Icn Simulationmentioning

confidence: 99%

Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept

Yokota

Ootsu

Ohkawa

2019

IEICE Trans. Inf. & Syst.

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A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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