Damped transient power clamps for improved ESD protection of CMOS

Hunter, Bradford L.; Butka, Brian

doi:10.1016/j.microrel.2005.05.006

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…Although simple in operation, the basic RC-triggered ESD protection circuit shown in Figure 3 is prone to oscillation due to employing only one timing element [6]. This can be explained as follows: once a fast rise on the supply node is detected, M BIGF ET is triggered.…”

Section: Review Of Rc-triggered Esd Protection Circuitsmentioning

confidence: 99%

An RC-triggered ESD clamp for high-voltage BCD CMOS processes

Koçer¹

2017

Turk J Elec Eng & Comp Sci

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This paper presents a novel RC-triggered, field-effect transistor (FET)-based power clamp that can be used in high-voltage complementary metal oxide semiconductor (CMOS) processes. A simple two-stage design provides a fast trigger while keeping the clamp transistor on for much longer than the triggering duration without the need for an additional digital latching circuit. As the presented technique does not require any digital circuits, it is especially useful in bipolar-CMOS-DMOS (BCD) processes, where the implementation of digital blocks is difficult due to the limited gateto-source voltage of the laterally diffused metal oxide semiconductor (LDMOS) transistors. The proposed architecture is implemented in a 0.25-µ m BCD process offered by TSMC. Simulation results show that Class 3A-level electrostatic discharge (ESD) protection can be achieved with an 8-mm-wide device while keeping all gate-to-source voltage values below the recommended 5-V limit. As the circuit operation depends on the well-modeled transient behavior of transistors, the proposed technique can be extended to other ESD ratings and can also be migrated to other processes without the need of extensive hardware verification.

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Section: Review Of Rc-triggered Esd Protection Circuitsmentioning

confidence: 99%

An RC-triggered ESD clamp for high-voltage BCD CMOS processes

Koçer¹

2017

Turk J Elec Eng & Comp Sci

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“…Another valuable method to implement a delay element is presented in Ref. [12]. The gate voltage of the clamp MOSFET is charged to "1" under the ESD event, and the gate parasitic capacitance stores quantities of charges.…”

Section: Design Of the Delay Elementmentioning

confidence: 99%

A novel high performance ESD power clamp circuit with a small area

Yang¹,

Liu²,

Li³

et al. 2012

J. Semicond.

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A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-m process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 s delay time and a 2.14 s turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.

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ESD Power Clamps

2008

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

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Damped transient power clamps for improved ESD protection of CMOS

Cited by 6 publications

References 2 publications

An RC-triggered ESD clamp for high-voltage BCD CMOS processes

An RC-triggered ESD clamp for high-voltage BCD CMOS processes

A novel high performance ESD power clamp circuit with a small area

ESD Power Clamps

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