DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches

Due to the technological advancements in the last few decades, several applications have emerged that demand more computing power and on-chip and off-chip memories. However, the scaling of memory technologies is not at par with computing throughput of modern day multi-core processors. Conventional memory technologies such as SRAM and DRAM have technological limitations to meet large on-chip memory requirements owing to their low packaging density and high leakage power. In order to meet the ever-increasing demand for memory, researchers came up with alternative solutions, such as emerging non-volatile memory technologies such as STT-RAM, PCM and ReRAM. However, these memory technologies have limited write endurance and high write energy. This emphasizes the need for a policy that will reduce the writes or distribute the writes uniformly across the memory thereby enhancing its lifetime by delaying the early wear out of memory cells due to frequent writes. We propose two techniques, Enhanced-Virtually Split Cache (E-ViSC) and Protean-Virtually Split Cache (P-ViSC), which dynamically adjust the cache configuration to distribute the writes uniformly across the memory to enhance the lifetime. Experimental studies show that E-ViSC and P-ViSC improve lifetime of NVM L2 caches by upto 2.31x and 1.97x respectively.

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DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches

Cited by 4 publications

References 11 publications

Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems

Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems

An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints

Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC

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