D5.3 - Electrical Characterization of the SiO2/4H-SiC Interface

Abstract

The interface trap density Dit is an important parameter to characterize the quality of the oxide/semiconductor interface. The low channel mobility (20 cm 2 /Vs for dry thermal oxidation) in silicon carbide-based MOS devices is mostly attributed to the high amount of interface traps. To attain high mobilities (>80 cm 2 /Vs), it is required to reduce the Dit to the range of 10 10 cm -2 eV -1 or below. Post oxidation annealing under nitrogen-based gaseous environment is known to reduce Dit, but still there is the requirement to reduce the Dit to reach those values of standard silicon/silicon-dioxide interfaces (10 10 -10 11 cm -2 eV -1 ). Oxides on SiC formed by plasma oxidation process instead of dry oxidation represents a promising technology, as it is known for exhibiting lower Dit values in the range of 10 10 -10 11 cm -2 eV -1 . However, the physics behind the plasma oxidation of 4H-SiC is not yet completely understood. In this work, we report first results about the enhanced oxidation rate and improved electrical characteristics when an oxygen plasma pre-treatment is implemented before the standard dry oxidation of 4H-SiC.