Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Ewart, Timothée; Delalondre, Fabien; Schürmann, Felix

doi:10.1007/978-3-319-07518-1_29

Cited by 7 publications

(5 citation statements)

References 6 publications

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“…Unfortunately, auto-vectorization performance using other compilers (e.g., GCC, clang) has been suboptimal or impossible for the CoreNEURON kernels, even on x86 hardware platforms. This was previously tested on Intel Skylake and Intel KNL [17].…”

Section: A Neuron Coreneuron and Nmodlmentioning

confidence: 99%

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Criado

García-Gasulla

Kumbhar

et al. 2020

2020 IEEE International Conference on Cluster Computing (CLUSTER)

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model of a rat hippocampus CA1 1. This model has about 447 thousand neurons, 304 million compartments, and 990 million synapses. To study such models at different scales, the community has developed various simulation software such as NEURON [1] for morphologically detailed neuron models, NEST [2] for point neuron models, and STEPS [3] for simulations at the molecular level. The simulation of morphologically detailed neuronal circuits like rat hippocampus CA1 is computationally expensive and requires access to a large computing cluster. Analyzing and optimizing such simulation software's performance on different hardware platforms is essential for delivering scientific results faster, and reducing the computational cost of such large scale simulations. In this paper, we present our efforts to analyze the performance of CoreNEURON [4], a compute engine of widely used NEURON simulator. Specifically, by using newly developed NMODL source to source compiler framework [5] with ISPC backend [6], we analyzed different performance metrics to evaluate Intel and Arm platforms. For decades scientific computing has been associated with mostly a single architecture, Intel x86. Since November 2018, the Armv8 architecture is part of the Top500 list 2 with the Astra supercomputer [7]. In June 2020, Fugaku by Fujitsu powered by the Arm Instruction Set Architecture (ISA), has been ranked as the fastest supercomputer in the world. Therefore, a valid question is how well complex applications such as neural simulations behave on high-performance systems powered by different architectures? There are several approaches in the literature [8], [9], mostly targeting Arm mobile SoCs. We employ server-grade Arm CPUs similar to [10], [11], but evaluating a different workflow. We isolated three layers that can affect the performance

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Section: A Neuron Coreneuron and Nmodlmentioning

confidence: 99%

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Criado

García-Gasulla

Kumbhar

et al. 2020

2020 IEEE International Conference on Cluster Computing (CLUSTER)

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“…It simplifies the generation of all polynomial evaluations and the code is generic. The algorithms are successively instantiated with the basic type double and a vector class from Ewart et al [2014] or any of those from Pohl et al [2016]. To control the quality of our ASM, at least on an x86 platform, we extract the DAG (Figure 2) using the IACA tool, for example for the evaluation of the first-order Horner method on a polynomial of degree 10.…”

Section: Programming Modelmentioning

confidence: 99%

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e ^x

Ewart

Cremonesi

Schürmann

et al. 2020

ACM Trans. Math. Softw.

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The evaluation of small degree polynomials is critical for the computation of elementary functions. It has been extensively studied and is well documented. In this article, we evaluate existing methods for polynomial evaluation on superscalar architecture. In addition, we have completed this work with a factorization method, which is surprisingly neglected in the literature. This work focuses on out-of-order Intel processors, amongst others, of which computational units are available. Moreover, we applied our work on the elementary function e x that requires, in the current implementation, an evaluation of a polynomial of degree 10 for a satisfying precision and performance. Our results show that the factorization scheme is the fastest in benchmarks, and that latency and throughput are intrinsically dependent on each other on superscalar architecture.

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“…However, few works propose to restructure existing data, in codes written in C or Fortran. This abstraction layer is also provided by libraries, hiding in particular the complexity of AoSoA layouts with SIMDization to the user (Cyme [5], Boost:SIMD or Kokkos [4], to name a few). The StructSlim profiler [15] helps programmers into data restructuring through structure splitting.…”

Section: Related Workmentioning

confidence: 99%

Rewriting System for Profile-Guided Data Layout Transformations on Binaries

Haine

Aumage²,

Barthou

2017

Lecture Notes in Computer Science

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Abstract. Careful data layout design is crucial for achieving high performance. However exploring data layouts is time-consuming and errorprone, and assessing the impact of a layout transformation on performance is difficult without performing it. We propose to guide application programmers through data layout restructuring by providing a comprehensive multidimensional description of the initial layout, built from trace analysis, and then by giving a performance evaluation of the transformations tested and an expression of each transformed layout. The programmer can limit the exploration to layouts matching some patterns. We apply this method to two multithreaded applications. The performance prediction of multiple transformations matches within 5% the performance of hand-transformed layout code.

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Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Cited by 7 publications

References 6 publications

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e ^x

Rewriting System for Profile-Guided Data Layout Transformations on Binaries

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Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Cited by 7 publications

References 6 publications

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e x

Rewriting System for Profile-Guided Data Layout Transformations on Binaries

Contact Info

Product

Resources

About

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e ^x