Cycle-Accurate Network on Chip Simulation with Noxim

Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide

doi:10.1145/2953878

Cited by 178 publications

(56 citation statements)

References 25 publications

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“…We evaluate the performance of the proposed low-latency adaptive router using cycle-accurate simulator Noxim [53] and many-core simulator Sniper [9]. The baseline is a three-cycle (including LT) adaptive router [15].…”

Section: Discussionmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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Abstract:To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs).

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Section: Discussionmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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“…To assess the tightness of the delay bounds yielded by G-BATA, we consider herein simulation results using Noxim simulator engine [25]. We have configured Noxim to control the traffic pattern using the provided traffic pattern file option.…”

Section: Tightness Analysismentioning

confidence: 99%

Graph-Based Approach for Buffer-Aware Timing Analysis of Heterogeneous Wormhole NoCs Under Bursty Traffic

Giroudot¹,

Mifdaoui²

2020

IEEE Access

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This paper addresses the problem of worst-case timing analysis of heterogeneous wormhole NoCs, i.e., routers with different buffer sizes and transmission speeds, when consecutivepacket queuing (CPQ) occurs. The latter means that there are several consecutive packets of one flow queuing in the network. This scenario happens in the case of bursty traffic but also for non-schedulable traffic. Conducting such an analysis is known to be a challenging issue due to the sophisticated congestion patterns when enabling backpressure mechanisms. We tackle this problem through extending the applicability domain of our previous work for computing maximum delay bounds using Network Calculus, called Buffer-aware worst-case Timing Analysis (BATA). We propose a new Graph-based approach to improve the analysis of indirect blocking due to backpressure, while capturing the CPQ effect and keeping the information about dependencies between flows. Furthermore, the introduced approach improves the computation of indirect-blocking delay bounds in terms of complexity and ensures the safety of these bounds even for nonschedulable traffic. We provide further insights into the tightness and complexity issues of worst-case delay bounds yielded by the extended BATA with the Graph-based approach, denoted G-BATA. Our assessments show that the complexity has decreased by up to 100 times while offering an average tightness ratio of 71%, with reference to the basic BATA. Finally, we evaluate the yielded improvements with G-BATA for a realistic use case against a recent state-of-the-art approach. This evaluation shows the applicability of G-BATA under more general assumptions and the impact of such a feature on the tightness and computation time.

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“…• buffer size for values 1,2,3,4,6,8,12,16,32,48,64 flits; • total payload (including header) for values 2, 4, 8, 16, 64, 96, 128 flits; • flow rate for values between 1% and 40% of the total link capacity (so that the total utilization rate on any link remains below 100%). To achieve this aim, we consider the configuration described on Table 1 and Figure 3.…”

Section: Tightness Analysismentioning

confidence: 99%

Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip

Giroudot

Mifdaoui

2019

Proceedings of the 27th International Conference on Real-Time Networks and Systems

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This paper addresses the problem of worst-case timing analysis in wormhole Networks-On-Chip (NoCs). We consider our previous work [5] for computing maximum delay bounds using Network Calculus, called the Buffer-Aware Worst-case Timing Analysis (BATA). The latter allows the computation of delay bounds for a large panel of wormhole NoCs, e.g., handling priority-sharing, Virtual Channel Sharing and buffer backpressure.In this paper, we provide further insights into the tightness and computation issues of the worst-case delay bounds yielded by BATA. Our assessment shows that the gap between the computed delay bounds and the worst-case simulation results is reasonably small (70% tighness on average). Furthermore, BATA provides good delay bounds for medium-scale configurations within less than one hour. Finally, we evaluate the yielded improvements with BATA for a realistic use-case against a recent state-of-the-art approach. This evaluation shows the applicability of BATA under more general assumptions and the impact of such a feature on the tightness and computation time.

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Cycle-Accurate Network on Chip Simulation with Noxim

Cited by 178 publications

References 25 publications

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Graph-Based Approach for Buffer-Aware Timing Analysis of Heterogeneous Wormhole NoCs Under Bursty Traffic

Tightness and computation assessment of worst-case delay bounds in wormhole networks-on-chip

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