2017
DOI: 10.1117/12.2262076
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Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies

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Cited by 2 publications
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“…The HKMG process is divided into two camps: the Gate first process represented by IBM and the Gate last process represented by Intel in the semiconductor industry. 5,6 HKMG Gate last process is the mainstream process route of HKMG process; 7 The manufacturing technology of metal gate structure is the key technology of HKMG back gate process; 8 The chemical-mechanical polishing (CMP) technology of metal gate is a breakthrough in the upgrading of HKMG process technology, 9,10 and mainly refers to the CMP technology of Al gate in the back-gate process, and the CMP technology of Al gate will become an important breakthrough in the future patent layout and technology upgrading in this field. 11,12 Compared with polysilicon gates, [13][14][15] Al gates have good conductivity, provide a stronger gate electric field, and effectively reduce gate capacitance.…”
mentioning
confidence: 99%
“…The HKMG process is divided into two camps: the Gate first process represented by IBM and the Gate last process represented by Intel in the semiconductor industry. 5,6 HKMG Gate last process is the mainstream process route of HKMG process; 7 The manufacturing technology of metal gate structure is the key technology of HKMG back gate process; 8 The chemical-mechanical polishing (CMP) technology of metal gate is a breakthrough in the upgrading of HKMG process technology, 9,10 and mainly refers to the CMP technology of Al gate in the back-gate process, and the CMP technology of Al gate will become an important breakthrough in the future patent layout and technology upgrading in this field. 11,12 Compared with polysilicon gates, [13][14][15] Al gates have good conductivity, provide a stronger gate electric field, and effectively reduce gate capacitance.…”
mentioning
confidence: 99%
“…The tolerance for within-wafer non-uniformity (WIWNU) and within-die (WIDNU) has been reduced. [8][9][10][11][12] Advanced 3D integrations require a high material removal rate (RR) for thick oxide films along with high planarization and low dishing. 13 CMP pad plays a vital role in achieving planarity as it makes direct contact with the wafer surface to remove chemically-modified material from the wafer surface.…”
mentioning
confidence: 99%