Current reused LC VCOs

Oh, Nam-Jin; Lee, Sang‐Gug

doi:10.1109/lmwc.2005.858993

Cited by 34 publications

(4 citation statements)

References 11 publications

(5 reference statements)

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“…The flicker noise in both the subthreshold and the superthreshold biased MOS transistors has no significant dependence on the gate voltage and is nearly equal in both regions. Thus, biasing the transistor in the subthreshold regime causes no improvement in the phase noise of oscillator in the 3 1 f region. However, using the large size MOS transistors leads to lower f K factor values, thus the phase noise in the 3 1 f region will be decreased.…”

Section: Phase Noise Considrations In the Subthreshold Regimementioning

confidence: 99%

“…The current reuse technique in [3] is a useful technique to reduce the power consumption, but since the differential output of VCO is non-symmetric, the phase noise is scarified. The dynamic threshold MOSFET technique is another way to reduce the supply voltage, but it can increase the sensitivity of circuit to power supply variations [4,5].…”

Section: Introductionmentioning

confidence: 99%

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Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

Fathi¹,

Nejad²

2013

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A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 µm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is −107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is −193.8 dB, which shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.

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Section: Phase Noise Considrations In the Subthreshold Regimementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

Fathi¹,

Nejad²

2013

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“…In RF frequency synthesizer, the VCO and the following divide-by-two cell work at the highest frequency, so they usually consume most of the power of the frequency synthesizer. The VCO and divide-by-two cell have been stacked in cascade to save the power consumed by the divide-by-two cell [2][3][4]. However, this method deteriorates the VCO phase noise performance, because the divide-by-two cell consumes voltage headroom which reduces the VCO output signal amplitude and the divide-by-two cell may interfere with the VCO.…”

Section: Introductionmentioning

confidence: 99%

A Current Reused Divided-by-Two Frequency Divider

Shi¹,

Huang²,

Liu³

et al. 2013

AMR

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In this paper, a low power dissipation divide-by-two frequency divider is presented. The master latch and the slave latch of the divide-by-two frequency divider are stacked in cascode to reuse the current. The frequency divider can operate with only half the current of a conventional divider. A divide-by-two frequency divider based on the proposed topology is designed and simulated in a 0.18μm 1P6M CMOS process. Simulation results show the frequency divider can operate up to 11GHz with only 0.66mW power dissipation under 1.8V supply voltage. And it also demonstrates good phase noise performance.

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“…Frequency synthesizers in 5G communication systems have phase-locked loop (PLL) techniques to form local oscillation (LO) signals to modulate and demodulate communication data. The important components of the techniques are the voltage-controlled oscillators (VCOs) to mainly supply LO signals [3][4][5]. For recent processes, the CMOS process has been well received to implement VCOs due to low power and cost features [6][7][8].…”

mentioning

confidence: 99%

CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

Chang

Liang

2022

Electronics Letters

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This study reports a voltage‐controlled oscillator (VCO) implemented in a 0.18‐μm CMOS process. By utilizing an inductive dual‐balance source degeneration (IDSD) technique with a current‐reused structure, the proposed VCO improves the phase noise and the power dissipation. The measured output frequency operates at 2.91–3.07 GHz by adjusting a control voltage from 0 to 1.1 V. The measured phase noise of the carrier of 2.94 GHz is −117.44 and −138.34 dBc/Hz at 1‐ and 10‐MHz offsets, respectively. The proposed VCO core consumes 2.38 mW from a supply voltage of 1.1 V. The figures‐of‐merits (FOMs) of the proposed VCO at 1‐ and 10‐MHz offsets are −183.04 dBc/Hz and −183.94 dBc/Hz, respectively.

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Current reused LC VCOs

Cited by 34 publications

References 11 publications

Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

A Current Reused Divided-by-Two Frequency Divider

CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

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