Current-mode subthreshold MOS circuits for analog VLSI neural systems

Andreou, Andreas G.; Boahen, Kwabena; Pouliquen, Philippe O.; Pavasovic, A.; Jenkins, Robert E.; Strohbehn, K.

doi:10.1109/72.80331

Cited by 283 publications

(80 citation statements)

References 13 publications

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“…Local disturbance can potentially result in large variations [4]. There are three types of local disturbances across the die : random variations, edge eects and striation eects.…”

Section: Local Disturbancementioning

confidence: 99%

Statistical delay modeling in logic design and synthesis

Jyu

Malik

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay specications of manufactured circuits. In order to capture the impact of these variations on the delay behavior of these circuits we propose a pair of statistical delay m o dels for use in logic design. These models abstract the real variations from the process level and can be used for statistical delay analysis and optimization in logic design and synthesis while oering an eciency vs. accuracy tradeo.

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“…Local disturbance can potentially result in large variations [4]. There are three types of local disturbances across the die : random variations, edge eects and striation eects.…”

Section: Local Disturbancementioning

confidence: 99%

Statistical delay modeling in logic design and synthesis

Jyu

Malik

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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“…Even in low-power applications where MOS devices are mostly biased in subthreshold regime, current-mode circuits exhibit a good power-speed performance [19]- [21].…”

Section: B Power Scalable Analog Circuitsmentioning

confidence: 99%

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits

Tajalli

Leblebici

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold sourcecoupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating with ultra-low power dissipation, because of similar basis for constructing analog and digital parts, a common power management unit could be used for optimizing the power-performance of the entire mixed-signal system. Some circuit examples have been provided to show the performance of the proposed circuits in practice.

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“…The integration (INT) block uses another instance of the DPI circuit to integrate the error current over time, producing the I ie current. The proportional (PROP) block uses a translinear multiplier [18] to multiply the I error current by constant scaling factors set by V np and V dp , producing the I pe current. The control circuit acts on the V thr bias voltage, which can be connected globally to all DPI synapses afferent to the neuron, to scale their outputs via the I g current.…”

Section: Analog Vlsi Implementation Of the Homeostatic Control Amentioning

confidence: 99%

Implementing homeostatic plasticity in VLSI networks of spiking neurons

Bartolozzi

Nikolayeva

Indiveri

2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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Homeostatic plasticity acts to stabilize firing activity in neural systems, ensuring a homogeneous computational substrate despite the inherent differences among neurons and their continuous change. These types of mechanisms are extremely relevant for any physical implementation of neural systems. They can be used in VLSI pulse-based neural networks to automatically adapt to chronic input changes, device mismatch, as well as slow systematic changes in the circuitpsilas functionality (e.g. due to temperature drifts). In this paper we propose analog circuits for implementing homeostatic plasticity mechanisms in VLSI spiking neural networks, compatible with local spike-based learning mechanisms. We show experimental results where a homeostatic control is implemented as a hybrid SoftWare/HardWare (SW/HW) solution, and present analog circuits for a complete on-chip stand-alone solution, validated by circuit simulations. Abstract-Homeostatic plasticity acts to stabilize firing activity in neural systems, ensuring a homogeneous computational substrate despite the inherent differences among neurons and their continuous change. These types of mechanisms are extremely relevant for any physical implementation of neural systems. They can be used in VLSI pulse-based neural networks to automatically adapt to chronic input changes, device mismatch, as well as slow systematic changes in the circuit's functionality (e.g. due to temperature drifts). In this paper we propose analog circuits for implementing homeostatic plasticity mechanisms in VLSI spiking neural networks, compatible with local spike-based learning mechanisms. We show experimental results where a homeostatic control is implemented as a hybrid SoftWare/HardWare (SW/HW) solution, and present analog circuits for a complete on-chip stand-alone solution, validated by circuit simulations.

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Current-mode subthreshold MOS circuits for analog VLSI neural systems

Cited by 283 publications

References 13 publications

Statistical delay modeling in logic design and synthesis

Statistical delay modeling in logic design and synthesis

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits

Implementing homeostatic plasticity in VLSI networks of spiking neurons

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