Current-mode signaling in deep submicrometer global interconnects

Bashirullah, Rizwan; Liu, Wentai; Cavin, Ralph K.

doi:10.1109/tvlsi.2003.812366

Cited by 70 publications

(42 citation statements)

References 13 publications

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“…This result matches the expectations of relative voltage and current mode performance from [33]. Therefore, the current mode commu- nication presented in this paper is preferred over voltage mode channels.…”

Section: E Performancesupporting

confidence: 88%

Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

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Section: E Performancesupporting

confidence: 88%

Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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“…The use of current sensing technique allows highly capacitive bit lines to be clamped at a fixed voltage, thus allowing faster sensing. Since large capacitance associated with the bit lines are not charged or discharged, this technique consumes less power [8], [19].…”

Section: Differential Rc Current Mode Signalingmentioning

confidence: 99%

A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

Venkataiah¹,

Tejaswi²

2015

IJCA

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The aggressive technology scaling in VLSI leads to decrease the size of chip. Such continual miniaturization of VLSI devices has strong impact on interconnects in several ways. Interconnects in high speed applications suffer from crosstalk, signal delay and ground noise, causing degradation of system performance. Thus interconnects are becoming a limiting factor in determining circuit performance. This paper presents a comparative study on different interconnect circuit techniques for on chip interconnects. We have compared different circuit structure by placing on RC and RLC interconnects. In this delay benefit for current sensing increases with an increase in wire width. Unlike repeaters, current sensing does not require placement of buffers along the wire and it eliminates any placement constraints. Out of all these techniques a differential RLC current mode signaling circuit insertion has offered the less amount of energy. All the circuits are simulated and compared different parameters such as power, delay and energy by using micro wind in 45nm technology.

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“…This leads to large transient currents consuming more power, larger delay, and it also generates power-supply noise [11]. The routing area (extra devices and control signal) and power resources.…”

Section: Current Mode Signaling (Cms) For Interconnect Delay Redumentioning

confidence: 99%

A Survey Addressing on High Performance On-Chip VLSI Interconnect

Yousuff¹,

Hasan²,

Galib³

2013

International Journal of Electronics and Telecommunications

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Abstract-With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.

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Current-mode signaling in deep submicrometer global interconnects

Cited by 70 publications

References 13 publications

Asynchronous Current Mode Serial Communication

Asynchronous Current Mode Serial Communication

A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

A Survey Addressing on High Performance On-Chip VLSI Interconnect

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