Current mismatch in paralleled phases of high power SiC modules due to threshold voltage unsymmetry and different gate-driver concepts

Horff, Roman; Bertelshofer, Teresa; März, Andreas; Bakran, Mark-M.

doi:10.1109/epe.2016.7695409

Cited by 9 publications

(6 citation statements)

References 5 publications

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“…4) Calculation Time: We evaluated the calculation time required to extract the dominant parameters by the conventional and proposed methods using (2) and (15). Table IX summarizes the conditions used in calculating T conv and T prop .…”

Section: Resultsmentioning

confidence: 99%

“…Fig.14(b)shows the results of applying the determined dominant model parameters. The selected model parameters reproduced each energy loss variation well, improving the accuracy of the standard deviation and the range error to 0.82% and 0.91%, respectively.We conclude that the dominant parameters determined by the proposed method are valid for practical situations when non-ideal conditions such as uneven parasitic inductance and temperature imbalance are considered.4) Calculation Time: We evaluated the calculation time required to extract the dominant parameters by the conventional and proposed methods using (2) and(15). TableIXsummarizes the conditions used in calculating T conv and T prop .…”

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confidence: 99%

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Dominant Model-Parameter Determination for the Analysis of Current Imbalance Across Paralleled Power Transistors

Nakamura

Shintani

Satō

2023

IEEE Trans. Power Electron.

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This paper proposes a new sensitivity-based analytical equation, the n-devices forward propagation of variance (NFPV). Using the proposed NFPV equation, the dominant device model parameters-essential for accurate analysis of energy-loss variation due to the current imbalance across paralleled power transistors from statistical parameter variations-are efficiently determined. The proposed method with the NFPV equation is faster than conventional methods that use Monte Carlo simulation. We conducted experimental validation using the measured current-voltage characteristics of commercially available 100 silicon MOSFETs and 300 silicon carbide MOSFETs. The results show that the proposed NFPV-based method efficiently finds the dominant device model parameters, which are sufficient and necessary to reproduce the energy-loss variation, regardless of the number of parallel transistors. The results also show that the determined dominant device model parameters are valid under practical situations, such as uneven parasitic inductances and device temperature imbalance among paralleled transistors. The proposed method determines the dominant device model parameters 9.33 times faster than the conventional method while maintaining the same accuracy. Additionally, we demonstrate that, compared with the conventional method, an increase in the number of candidate statistical model parameters increases the efficiency of the proposed method.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Dominant Model-Parameter Determination for the Analysis of Current Imbalance Across Paralleled Power Transistors

Nakamura

Shintani

Satō

2023

IEEE Trans. Power Electron.

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“…However, when paralleling two or more SiC MOSFETs, their currents may not be balanced due to the statistical fluctuations of the on-state resistance (Ron) and threshold voltage (VTH) from sample to sample. This phenomenon can drastically reduce the reliability of the entire power system [4]. Previous works [5], [6] have suggested different feedback techniques for balancing drain currents during switching transients.…”

Section: Introductionmentioning

confidence: 99%

High-temperature validated SiC power MOSFET model for flexible robustness analysis of multi-chip structures

Riccio

d’Alessandro

Romano

et al. 2018

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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This paper presents a statistical analysis on the effect of parallel connection of SiC power MOSFETs in high current applications. To this purpose, a reliable temperaturedependent SPICE model is calibrated on static and dynamic experimental curves of 1.2kV-36A commercial SiC MOSFET. The statistical fluctuation of threshold voltage and on-resistance is evaluated on 20 device samples and modeled with Gaussian functions. The proposed analysis, based on SPICE electrothermal Monte Carlo simulations, is then aimed to improve the design of high current systems with multi-chip devices. Therefore, the study is focused on the evaluation of current and energy unbalance during device switching under inductive load. Results achieved for nominal switching condition and out-of-SOA current levels are discussed.

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“…However, current unbalance may arise because of paralleled switching devices, because of mismatched parasitic parameters, which vary according to the circuit layout. Moreover, the on‐resistance, gain and threshold voltage of the paralleled devices are not the same [7, 8]. The current unbalance can be reduced by designing the circuit in a symmetric layout, and by employing switching devices with identical characteristics.…”

Section: Introductionmentioning

confidence: 99%

Oscillation analysis and current peak reduction in paralleled SiC MOSFETs

Nanamori

Sugihara

Yamamoto

2018

IET Circuits, Devices & Systems

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Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.

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Current mismatch in paralleled phases of high power SiC modules due to threshold voltage unsymmetry and different gate-driver concepts

Cited by 9 publications

References 5 publications

Dominant Model-Parameter Determination for the Analysis of Current Imbalance Across Paralleled Power Transistors

Dominant Model-Parameter Determination for the Analysis of Current Imbalance Across Paralleled Power Transistors

High-temperature validated SiC power MOSFET model for flexible robustness analysis of multi-chip structures

Oscillation analysis and current peak reduction in paralleled SiC MOSFETs

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